HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39030 )
Change subject: src: capitalize 'APIC' ......................................................................
src: capitalize 'APIC'
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/cpu.c M src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/broadwell/smi.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/lynxpoint/smi.c 14 files changed, 22 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39030/1
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 30d2cca..0bfe4c1 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -221,7 +221,7 @@ cpu->ops = driver ? driver->ops : NULL; }
-/* Keep track of default apic ids for SMM. */ +/* Keep track of default APIC ids for SMM. */ static int cpus_default_apic_id[CONFIG_MAX_CPUS];
/* diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index 3530801..9411b5f 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -22,11 +22,11 @@
/* Methods called by run-time generated SSDT Processor objects */ Method(CPMA, 1, NotSerialized) { - // _MAT method - create an madt apic buffer + // _MAT method - create an madt APIC buffer // Arg0 = Processor ID = Local APIC ID // Local0 = CPON flag for this cpu Store(DerefOf(Index(CPON, Arg0)), Local0) - // Local1 = Buffer (in madt apic form) to return + // Local1 = Buffer (in madt APIC form) to return Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) // Update the processor id, lapic id, and enable/disable status Store(Arg0, Index(Local1, 2)) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 074b4b9..27e6daf 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -861,7 +861,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 794428b..1463e5f 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -887,7 +887,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2295cd6..7c9cde2 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -865,7 +865,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 3e04ec3..f6affcc 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -872,7 +872,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index cf4d78b..2442e36 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1133,7 +1133,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 2fed005..1161325 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -197,49 +197,49 @@ .io_sel = GPIO_DIR_INPUT, \ .is_gpio = 1 }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELHIGH_NO_PULL \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELLOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEHIGH_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEBOTH_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 2bdeecc..2beab65 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -73,7 +73,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index dc53220..e85241c 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -306,7 +306,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5f73f41..2509e0a 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -112,7 +112,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index 1fe40b6..ce76db0 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -11,7 +11,7 @@ * GNU General Public License for more details. */
-/* for io apic 1461 */ +/* for io APIC 1461 */ #define MBAR 0x10 #define ABAR 0x40
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4fbf329..1f4aa501a 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -43,8 +43,8 @@ uint32_t memoryBase; int apic_index, apic_id;
- volatile uint32_t *pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t *pWindowRegister; /* io apic io memory space data address */ + volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */ + volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */
apic_index = num_p64h2_ioapics; num_p64h2_ioapics++; diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index e5c390e..8b6e4e4 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -77,7 +77,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39030 )
Change subject: src: capitalize 'APIC' ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/39030/1/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl:
https://review.coreboot.org/c/coreboot/+/39030/1/src/mainboard/emulation/qem... PS1, Line 29: madt This should be MADT (handle in another change)
https://review.coreboot.org/c/coreboot/+/39030/1/src/mainboard/emulation/qem... PS1, Line 31: lapic This is "Local APIC". Maybe you want to update it as well?
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39030
to look at the new patch set (#2).
Change subject: src: capitalize 'APIC' ......................................................................
src: capitalize 'APIC'
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/arch/x86/cpu.c M src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/broadwell/smi.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/lynxpoint/smi.c 14 files changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39030/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39030 )
Change subject: src: capitalize 'APIC' ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39030/1/src/mainboard/emulation/qem... File src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl:
https://review.coreboot.org/c/coreboot/+/39030/1/src/mainboard/emulation/qem... PS1, Line 29: madt
This should be MADT (handle in another change)
Ack
https://review.coreboot.org/c/coreboot/+/39030/1/src/mainboard/emulation/qem... PS1, Line 31: lapic
This is "Local APIC". […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39030 )
Change subject: src: capitalize 'APIC' ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39030 )
Change subject: src: capitalize 'APIC' ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39030 )
Change subject: src: capitalize 'APIC' ......................................................................
src: capitalize 'APIC'
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/arch/x86/cpu.c M src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/broadwell/smi.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/lynxpoint/smi.c 14 files changed, 23 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 4c1bce0..8f8fdc1 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -211,7 +211,7 @@ cpu->ops = driver ? driver->ops : NULL; }
-/* Keep track of default apic ids for SMM. */ +/* Keep track of default APIC ids for SMM. */ static int cpus_default_apic_id[CONFIG_MAX_CPUS];
/* diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index 3530801..e46611d 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -22,13 +22,13 @@
/* Methods called by run-time generated SSDT Processor objects */ Method(CPMA, 1, NotSerialized) { - // _MAT method - create an madt apic buffer + // _MAT method - create an madt APIC buffer // Arg0 = Processor ID = Local APIC ID // Local0 = CPON flag for this cpu Store(DerefOf(Index(CPON, Arg0)), Local0) - // Local1 = Buffer (in madt apic form) to return + // Local1 = Buffer (in madt APIC form) to return Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) - // Update the processor id, lapic id, and enable/disable status + // Update the processor id, Local APIC id, and enable/disable status Store(Arg0, Index(Local1, 2)) Store(Arg0, Index(Local1, 3)) Store(Local0, Index(Local1, 4)) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 3519ab0..642fc15 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -859,7 +859,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 96d71cd..fcd7ec1 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -886,7 +886,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2df105a..28502b0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -864,7 +864,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 855936a..0a1b0ba 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -871,7 +871,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8f23e68..05c5142 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1130,7 +1130,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index d6be80f..3c1e7f3 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -196,49 +196,49 @@ .io_sel = GPIO_DIR_INPUT, \ .is_gpio = 1 }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELHIGH_NO_PULL \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELLOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEHIGH_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, }
-/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEBOTH_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index b26700e..b1be1fa 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -71,7 +71,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 0de98ac..26dfc60 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -305,7 +305,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 25d3515..6e7463f 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -111,7 +111,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index 1fe40b6..ce76db0 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -11,7 +11,7 @@ * GNU General Public License for more details. */
-/* for io apic 1461 */ +/* for io APIC 1461 */ #define MBAR 0x10 #define ABAR 0x40
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4fbf329..1f4aa501a 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -43,8 +43,8 @@ uint32_t memoryBase; int apic_index, apic_id;
- volatile uint32_t *pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t *pWindowRegister; /* io apic io memory space data address */ + volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */ + volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */
apic_index = num_p64h2_ioapics; num_p64h2_ioapics++; diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index ed3c6cc..6aef493 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -76,7 +76,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)