John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41383 )
Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En ......................................................................
soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 23 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/41383/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e6e106d..0f1fca0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -212,10 +212,14 @@ FORCE_ENABLE, } CnviBtAudioOffload;
- /* Tcss */ + /* Tcss USB */ uint8_t TcssXhciEn; uint8_t TcssXdciEn;
+ /* Tcss DMA */ + uint8_t TcssDma0En; + uint8_t TcssDma1En; + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 683172f..d76c4a1 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -30,6 +30,10 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
+#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) #define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) @@ -40,9 +44,15 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
-#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) +#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3)
/* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 6f0f06d..cd51e07 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -111,10 +111,14 @@ /* Image clock: disable all clocks for bypassing FSP pin mux */ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
- /* Tcss */ + /* Tcss USB */ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn;
+ /* TCSS DMA */ + m_cfg->TcssDma0En = config->TcssDma0En; + m_cfg->TcssDma1En = config->TcssDma1En; + /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); if (dev)
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41383 )
Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En ......................................................................
Patch Set 1: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41383 )
Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Nick Vaccaro, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41383
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En ......................................................................
soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 23 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/41383/4
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41383 )
Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En ......................................................................
soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 23 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c98fb66..3047037 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -213,10 +213,14 @@ FORCE_ENABLE, } CnviBtAudioOffload;
- /* Tcss */ + /* Tcss USB */ uint8_t TcssXhciEn; uint8_t TcssXdciEn;
+ /* Tcss DMA */ + uint8_t TcssDma0En; + uint8_t TcssDma1En; + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 683172f..d76c4a1 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -30,6 +30,10 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
+#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) #define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) @@ -40,9 +44,15 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
-#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_TCSS 0x0d +#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) +#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) +#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) +#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) +#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3)
/* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index a444623..ede5059 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -111,10 +111,14 @@ /* Image clock: disable all clocks for bypassing FSP pin mux */ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
- /* Tcss */ + /* Tcss USB */ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn;
+ /* TCSS DMA */ + m_cfg->TcssDma0En = config->TcssDma0En; + m_cfg->TcssDma1En = config->TcssDma1En; + /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); if (dev)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41383 )
Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41383/6/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/41383/6/src/soc/intel/tigerlake/rom... PS6, Line 119: config->TcssDma0En I don't think you need a separate chip config for this. You can simply use SA_DEVFN_TCSS_DMA0 and dev->enabled.
https://review.coreboot.org/c/coreboot/+/41383/6/src/soc/intel/tigerlake/rom... PS6, Line 120: TcssDma1En Same here. Use SA_DEVFN_TCSS_DMA1.
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Furquan Shaikh (Code Review) -
John Zhao (Code Review)
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Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)