Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34970 )
Change subject: intel/car: Use common TS_START_ROMSTAGE ......................................................................
intel/car: Use common TS_START_ROMSTAGE
This timestamp for unintentionally removed from cpu/haswell and cpu/model_1067x platforms with commit.
Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/car/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 2 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34970/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 9298676..5a1a4c4 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -83,6 +83,8 @@
asmlinkage void car_stage_entry(void) { + timestamp_add_now(TS_START_ROMSTAGE); + /* Assumes the hardware was set up during the bootblock */ console_init();
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2c28339..7e369f4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -47,7 +47,6 @@ #include <soc/systemagent.h> #include <spi_flash.h> #include <timer.h> -#include <timestamp.h> #include "chip.h"
static const uint8_t hob_variable_guid[16] = { @@ -199,8 +198,6 @@ struct chipset_power_state *ps = pmc_get_power_state(); const void *new_var_data;
- timestamp_add_now(TS_START_ROMSTAGE); - soc_early_romstage_init();
s3wake = pmc_fill_power_state(ps) == ACPI_S3; diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 5711c15..fb5e42b 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -28,7 +28,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h>
#include "../chip.h"
@@ -137,7 +136,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS);
- timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 67ef2bb..a96f057 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -29,7 +29,6 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> -#include <timestamp.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -121,7 +120,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS);
- timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2412f22..5388858 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -32,7 +32,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h> #include <security/vboot/vboot_common.h>
#include "../chip.h" @@ -148,7 +147,6 @@ systemagent_early_init();
ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb();
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34970 )
Change subject: intel/car: Use common TS_START_ROMSTAGE ......................................................................
Patch Set 2: Code-Review+1
Hello Patrick Rudolph, HAOUAS Elyes, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34970
to look at the new patch set (#6).
Change subject: intel/car: Use common TS_START_ROMSTAGE ......................................................................
intel/car: Use common TS_START_ROMSTAGE
This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry.
Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/car/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 2 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/34970/6
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34970 )
Change subject: intel/car: Use common TS_START_ROMSTAGE ......................................................................
Patch Set 6: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34970 )
Change subject: intel/car: Use common TS_START_ROMSTAGE ......................................................................
intel/car: Use common TS_START_ROMSTAGE
This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry.
Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/car/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 2 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index ac81b02..547b121 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -87,6 +87,8 @@
asmlinkage void car_stage_entry(void) { + timestamp_add_now(TS_START_ROMSTAGE); + /* Assumes the hardware was set up during the bootblock */ console_init();
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2c28339..7e369f4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -47,7 +47,6 @@ #include <soc/systemagent.h> #include <spi_flash.h> #include <timer.h> -#include <timestamp.h> #include "chip.h"
static const uint8_t hob_variable_guid[16] = { @@ -199,8 +198,6 @@ struct chipset_power_state *ps = pmc_get_power_state(); const void *new_var_data;
- timestamp_add_now(TS_START_ROMSTAGE); - soc_early_romstage_init();
s3wake = pmc_fill_power_state(ps) == ACPI_S3; diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 5711c15..fb5e42b 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -28,7 +28,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h>
#include "../chip.h"
@@ -137,7 +136,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS);
- timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 67ef2bb..a96f057 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -29,7 +29,6 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> -#include <timestamp.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -121,7 +120,6 @@ /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS);
- timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2412f22..5388858 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -32,7 +32,6 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> -#include <timestamp.h> #include <security/vboot/vboot_common.h>
#include "../chip.h" @@ -148,7 +147,6 @@ systemagent_early_init();
ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb();
-
Aaron Durbin (Code Review) -
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)