Lijian Zhao (lijian.zhao@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15084
-gerrit
commit bc0044edc1dc981a3a1e33ae4776abf0c0360543 Author: Zhao, Lijian lijian.zhao@intel.com Date: Tue May 17 19:01:34 2016 -0700
soc/intel/apollolake: Add EMMC DLL API
Starting from 136_30,FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init.
Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian lijian.zhao@intel.com Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey andrey.petrov@intel.com Tested-by: Petrov, Andrey andrey.petrov@intel.com Reviewed-on: https://chromium.devtools.intel.com/7585 --- src/soc/intel/apollolake/chip.c | 3 +++ src/soc/intel/apollolake/chip.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 17bceec..95f1286 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -115,6 +115,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
+ if (cfg->emmc_tx_data_cntl1 != 0) + silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; + /* Our defaults may not match FSP defaults, so set them explicitly */ silconfig->AcpiBase = ACPI_PMIO_BASE; /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3d9f5bd..ef82c53 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -40,6 +40,40 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin;
+ /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_tx_cmd_cntl; + + /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_tx_data_cntl1; + + /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. + * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. + * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_tx_data_cntl2; + + /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. + * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. + * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_rx_cmd_data_cntl1; + + /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. + * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_rx_strobe_cntl; + + /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_rx_cmd_data_cntl2; + /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode;
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Lijian Zhao