Change in ...coreboot[master]: usbdebug: Sanity check PCI EHCI location

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30692

Change subject: usbdebug: Sanity check PCI EHCI location
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usbdebug: Sanity check PCI EHCI location

If requested EHCI function is not on bus 0, we would
need to open MMIO windows and configuration register
space for the connected upstream PCI bridge for it
to work. We don't plan to do so.

Change-Id: I7c1c60f9d9890dedfedc9d977faf5152ba362692
Signed-off-by: Kyösti Mälkki 
---
M src/drivers/usb/pci_ehci.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/30692/1

diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index e0f88ec..c051291 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -34,6 +34,10 @@
 {
    pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);

+	/* We only support controllers on bus 0. */
+	if (PCI_DEV2SEGBUS(dbg_dev) != 0)
+		return -1;
+
 #ifdef __SIMPLE_DEVICE__
    pci_devfn_t dev = dbg_dev;
 #else