Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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Patch Set 15:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/50996/comment/89cfd96e_595f7a43 
PS14, Line 9: The coreboot SMBus driver requires additional changes
please use col 72 ?

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/d5dee1e2_4a68dc0a 
PS14, Line 55: 		memcfg_init(m_cfg, mem_config, &ddr4_ddr5_spd_info, half_populated);
             : 		break;
isn't this is same as line 59-60 below ?

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/9c8aafa5_4dee89dd 
PS14, Line 222:        
tab please ?

https://review.coreboot.org/c/coreboot/+/50996/comment/12472474_5fd67375 
PS14, Line 225: 16
sizeof(spd_array) ?

https://review.coreboot.org/c/coreboot/+/50996/comment/4e7a7100_a71cdfe2 
PS14, Line 266:        
tab please ?