Change in coreboot[master]: soc/amd/common/lpc: Skip SERIRQ setup when using eSPI

[Marshall Dawson (Code Review)]

Hello Raul Rangel,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42896

to review the following change.

Change subject: soc/amd/common/lpc: Skip SERIRQ setup when using eSPI
......................................................................

soc/amd/common/lpc: Skip SERIRQ setup when using eSPI

BUG=b:157984427
TEST=check value of PMx054

Signed-off-by: Marshall Dawson 
Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 14 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42896/1

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 3ddedce..8aa74d2 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -24,6 +24,18 @@
 /* Most systems should have already enabled the bridge */
 void __weak soc_late_lpc_bridge_enable(void) { }

+static void setup_serirq(void)
+{
+	u8 byte;
+
+	/* Set up SERIRQ, enable continuous mode */
+	byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
+	if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
+		byte |= PM_SERIRQ_MODE;
+
+	pm_write8(PM_SERIRQ_CONF, byte);
+}
+
 static void lpc_init(struct device *dev)
 {
    u8 byte;
@@ -80,12 +92,8 @@
    /* Initialize i8254 timers */
    setup_i8254();

-	/* Set up SERIRQ, enable continuous mode */
-	byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
-	if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
-		byte |= PM_SERIRQ_MODE;
-
-	pm_write8(PM_SERIRQ_CONF, byte);
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		setup_serirq();
 }

static void lpc_read_resources(struct device *dev)

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42896 )

Change subject: soc/amd/common/lpc: Skip SERIRQ setup when using eSPI
......................................................................

Patch Set 1: Code-Review+2

[Marshall Dawson (Code Review)]

Marshall Dawson has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42896 )

Change subject: soc/amd/common/lpc: Skip SERIRQ setup when using eSPI
......................................................................

soc/amd/common/lpc: Skip SERIRQ setup when using eSPI

BUG=b:157984427
TEST=check value of PMx054

Signed-off-by: Marshall Dawson 
Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42896
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 14 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 5e18aad..deadfa2 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -25,6 +25,18 @@
 /* Most systems should have already enabled the bridge */
 void __weak soc_late_lpc_bridge_enable(void) { }

+static void setup_serirq(void)
+{
+	u8 byte;
+
+	/* Set up SERIRQ, enable continuous mode */
+	byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
+	if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
+		byte |= PM_SERIRQ_MODE;
+
+	pm_write8(PM_SERIRQ_CONF, byte);
+}
+
 static void lpc_init(struct device *dev)
 {
    u8 byte;
@@ -81,12 +93,8 @@
    /* Initialize i8254 timers */
    setup_i8254();

-	/* Set up SERIRQ, enable continuous mode */
-	byte = (PM_SERIRQ_NUM_BITS_21 | PM_SERIRQ_ENABLE);
-	if (!CONFIG(SERIRQ_CONTINUOUS_MODE))
-		byte |= PM_SERIRQ_MODE;
-
-	pm_write8(PM_SERIRQ_CONF, byte);
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		setup_serirq();
 }

static void lpc_read_resources(struct device *dev)