[M] Change in coreboot[main]: soc/amd/glinda/pcie_gpp.c: Add PCI routing table

[Felix Held (Code Review)]

Attention is currently required from: Maximilian Brune.

Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/85019?usp=email )

Change subject: soc/amd/glinda/pcie_gpp.c: Add PCI routing table
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Patch Set 1:

(1 comment)

Patchset:

PS1: 
either the fsp should provide a valid irq routing table hob or we should read the config that the fsp has applied from the registers; probalen with that is that the indices of the two sets of registers don't necessarily have a 1:1 mapping.
i think that having this config basically hard-coded in both fsp and coreboot has the potential for things to break when one side is changed, but the other isn't