Change in coreboot[master]: mb/intel/tglrvp: Add TGL UP4 RVP - coreboot-gerrit

6 Mar 2020

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39363 )
Change subject: mb/intel/tglrvp: Add TGL UP4 RVP
......................................................................
mb/intel/tglrvp: Add TGL UP4 RVP
Add initial TGL UP4 RVP build enviorment
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com
Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c
---
M src/mainboard/intel/tglrvp/Kconfig
M src/mainboard/intel/tglrvp/Kconfig.name
A src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc
A src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
A src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
A src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
6 files changed, 402 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/39363/1

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
index 5eec51e..2051a05 100644
--- a/src/mainboard/intel/tglrvp/Kconfig
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_INTEL_TGLRVP_UP3
+if BOARD_INTEL_TGLRVP_UP3 || BOARD_INTEL_TGLRVP_UP4
config BOARD_SPECIFIC_OPTIONS
    def_bool y
@@ -28,11 +28,13 @@
 config VARIANT_DIR
    string
    default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3
+	default "tglrvp_up4" if BOARD_INTEL_TGLRVP_UP4
config GBB_HWID
    string
    depends on CHROMEOS
-	default "TGLRVP" if BOARD_INTEL_TGLRVP_UP3
+	default "TGLRVPUP3" if BOARD_INTEL_TGLRVP_UP3
+	default "TGLRVPUP4" if BOARD_INTEL_TGLRVP_UP4
config MAINBOARD_PART_NUMBER
    string
diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name
index a2271f3..eb8e796 100644
--- a/src/mainboard/intel/tglrvp/Kconfig.name
+++ b/src/mainboard/intel/tglrvp/Kconfig.name
@@ -1,2 +1,5 @@
 config BOARD_INTEL_TGLRVP_UP3
-	bool "Tigerlake UP3 DDR4/LPDDR4 RVP"
+	bool "Tigerlake UP3 RVP"
+
+config BOARD_INTEL_TGLRVP_UP4
+	bool "Tigerlake UP4 RVP"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc
new file mode 100644
index 0000000..c272607
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019-2020 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
new file mode 100644
index 0000000..e61690e
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -0,0 +1,207 @@
+chip soc/intel/tigerlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+	register "SmbusEnable" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# M.2 Bluetooth
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port1
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"		# Type-C Port4
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"		# USB3/2 Type A port2
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port3
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port4
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Not used
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# USB3/USB2 Flex Connector
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	register "PrmrrSize" = "0x10000000"
+
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[10]" = "1"
+
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+
+	register "PcieClkSrcUsage[1]" = "0x2"
+	register "PcieClkSrcUsage[2]" = "0x3"
+	register "PcieClkSrcUsage[3]" = "0x8"
+
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+
+	# enabling EDP in PortA
+	register "DdiPortAConfig" = "1"
+
+	register "DdiPort1Hpd" = "1"
+	register "DdiPort1Ddc" = "1"
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "SerialIoGSpiMode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoGSpiCsMode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "SerialIoGSpiCsState" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+		[PchSerialIoIndexGSPI3] = 0,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoPci,
+	}"
+
+	#HD Audio
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHdaEnable" = "0"
+	register "PchHdaAudioLinkDmicEnable[0]" = "1"
+	register "PchHdaAudioLinkDmicEnable[1]" = "1"
+	register "PchHdaAudioLinkSspEnable[0]" = "1"
+	register "PchHdaAudioLinkSspEnable[1]" = "1"
+	# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
+	register "PchHdaIDispLinkTmode" = "2"
+	# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
+	register "PchHdaIDispLinkFrequency" = "4"
+	# Not disconnected/enumerable
+	register "PchHdaIDispCodecDisconnect" = "0"
+
+	device domain 0 on
+		#From EDS(575683)
+		device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y
+		device pci 02.0 on  end # Graphics
+		device pci 04.0 on  end # DPTF			0x9A03
+		device pci 05.0 on  end # IPU			0x9A19
+		device pci 06.0 on  end # PEG60			0x9A09
+		device pci 07.0 off end # TBT_PCIe0		0x9A23
+		device pci 07.1 off end # TBT_PCIe1		0x9A25
+		device pci 07.2 off end # TBT_PCIe2		0x9A27
+		device pci 07.3 off end # TBT_PCIe3		0x9A29
+		device pci 08.0 off end # GNA			0x9A11
+		device pci 09.0 off end # NPK			0x9A33
+		device pci 0a.0 off end # Crash-log SRAM	0x9A0D
+		device pci 0d.0 on  end # USB xHCI		0x9A13
+		device pci 0d.1 on  end # USB xDCI (OTG)	0x9A15
+		device pci 0d.2 off end # TBT DMA0		0x9A1B
+		device pci 0d.3 off end # TBT DMA1		0x9A1D
+		device pci 0e.0 on  end # VMD			0x9A0B
+
+		# From PCH EDS(576591)
+		device pci 10.2 off end # CNVi: BT		0xA0F5 - A0F7
+		device pci 10.6 off end # THC0			0xA0D0
+		device pci 10.7 off end # THC1			0xA0D1
+		device pci 12.0 off end # SensorHUB		0xA0FC
+		device pci 12.6 off end # GSPI2			0x34FB
+		device pci 13.0 off end # GSPI3			0xA0FD
+		device pci 14.0 on  end # USB3.1 xHCI 		0xA0ED
+		device pci 14.1 on  end # USB3.1 xDCI		0xA0EE
+		device pci 14.2 on  end # Shared RAM		0xA0EF
+		device pci 14.3 off end # CNVi: WiFi		0xA0F0 - A0F3
+		device pci 15.0 on  	# I2C0			0xA0E8
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "4"
+				register "imon_slot_no" = "5"
+				register "uid" = "0"
+				register "desc" = ""RIGHT SPEAKER AMP""
+				register "name" = ""MAXR""
+				device i2c 31 on end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "6"
+				register "imon_slot_no" = "7"
+				register "uid" = "1"
+				register "desc" = ""LEFT SPEAKER AMP""
+				register "name" = ""MAXL""
+				device i2c 32 on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5682""
+				register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)"
+				register "probed" = "1"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end	# I2C0
+		device pci 15.1 on  end # I2C1			0xA0E9
+		device pci 15.2 on  end # I2C2			0xA0EA
+		device pci 15.3 on  end # I2C3			0xA0EB
+		device pci 16.0 on  end # HECI1			0xA0E0
+		device pci 16.1 off end # HECI2			0xA0E1
+		device pci 16.2 off end # CSME			0xA0E2
+		device pci 16.3 off end # CSME			0xA0E3
+		device pci 16.4 off end # HECI3			0xA0E4
+		device pci 16.5 off end # HECI4			0xA0E5
+		device pci 17.0 on  end # SATA			0xA0D3
+		device pci 19.0 off end # I2C4			0xA0C5
+		device pci 19.1 on  end # I2C5			0xA0C6
+		device pci 19.2 on  end # UART2			0xA0C7
+		device pci 1c.0 off end # RP1			0xA0B8
+		device pci 1c.1 off end # RP2			0xA0B9
+		device pci 1c.2 on  end # RP3			0xA0BA
+		device pci 1c.3 on  end # RP4			0xA0BB
+		device pci 1c.4 off end # RP5			0xA0BC
+		device pci 1c.5 off end # RP6			0xA0BD
+		device pci 1c.6 off end # RP7			0xA0BE
+		device pci 1c.7 off end # RP8			0xA0BF
+		device pci 1d.0 on  end # RP9			0xA0B0
+		device pci 1d.1 off end # RP10			0xA0B1
+		device pci 1d.2 on  end # RP11			0xA0B2
+		device pci 1d.3 off end # RP12			0xA0B3
+		device pci 1e.0 off end # UART0			0xA0A8
+		device pci 1e.1 off end # UART1			0xA0A9
+		device pci 1e.2 off end # GSPI0			0xA0AA
+		device pci 1e.3 off end # GSPI1			0xA0AB
+		device pci 1f.0 on  end # eSPI			0xA080 - A09F
+		device pci 1f.1 on  end # P2SB			0xA0A0
+		device pci 1f.2 on  end # PMC			0xA0A1
+		device pci 1f.3 on  end # Intel HD audio	0xA0C8-A0CF
+		device pci 1f.4 on  end # SMBus			0xA0A3
+		device pci 1f.5 on  end # SPI			0xA0A4
+		device pci 1f.6 off end # GbE			0x15E1/0x15E2
+		device pci 1f.7 off end # TH			0xA0A6
+	end
+end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
new file mode 100644
index 0000000..46ed5a2
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* PCH M.2 SSD */
+	PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+
+	/* Camera */
+	PAD_CFG_GPO(GPP_B23, 0, PLTRST),
+	PAD_CFG_GPO(GPP_C15, 0, PLTRST),
+	PAD_CFG_GPO(GPP_R6, 0, PLTRST),
+	PAD_CFG_GPO(GPP_H12, 0, PLTRST),
+
+	/* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
+	PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
+
+	/* ISH UART0 RX/TX */
+	PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
+
+	/* ISH I2C0 */
+	PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
+
+	/* ISH GPI 0-6 */
+	PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
+	PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
+
+	/*Audio */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+	PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+	/*Audio */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),   /* I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),   /* I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),   /* I2S0_HP_RX */
+
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),  /* I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),   /* I2S1_SPKR_TX */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),   /* I2S1_SPKR_RX */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),   /* I2S1_SPKR_SFRM */
+
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),   /* SNDW0_HP_CLK */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),   /* SNDW0_HP_DATA */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),   /* SNDW1_SPKR_CLK */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),   /* SNDW1_SPKR_DATA */
+
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),   /* DMIC1_CLK */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),   /* DMIC1_DATA */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),   /* DMIC0_CLK */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),   /* DMIC0_DATA */
+
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
new file mode 100644
index 0000000..67979b6
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/memory.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <baseboard/variants.h>
+#include <intelblocks/mp_init.h>
+
+size_t __weak variant_memory_sku(void)
+{
+	return 0;
+}
+
+static const struct mb_lpddr4x_cfg mem_config = {
+	/* DQ byte map */
+	.dq_map = {
+	{  0,  1,  6,  7,  3,  2,  5,  4,    /* Byte 0 */
+	  15,  8,  9, 14, 12, 11, 10, 13 },  /* Byte 1 */
+	{ 11, 12,  8, 15,  9, 14, 10, 13,    /* Byte 2 */
+	   3,  4,  7,  0,  6,  1,  5,  2 },  /* Byte 3 */
+	{  4,  5,  3,  2,  7,  1,  0,  6,    /*	Byte 4 */
+	  11, 10, 12, 13,  8,  9, 14, 15 },  /* Byte 5 */
+	{ 12, 11,  8, 13, 14, 15,  9, 10,    /* Byte 6 */
+	   4,  7,  3,  2,  1,  6,  0,  5 },  /* Byte 7 */
+	{ 11, 10,  9,  8, 12, 13, 15, 14,    /* Byte 0 */
+	   4,  5,  6,  7,  3,  2,  0,  1 },  /* Byte 1 */
+	{  0,  7,  1,  6,  3,  5,  2,  4,    /* Byte 2 */
+	   9,  8, 10, 11, 14, 15, 13, 12 },  /* Byte 3 */
+	{  4,  5,  6,  1,  3,  2,  7,  0,    /* Byte 4 */
+	  10, 13, 12, 11, 14,  9, 15,  8 },  /* Byte 5 */
+	{ 10, 12,  9, 15,  8, 11, 13, 14,    /* Byte 6 */
+	   3,  4,  1,  2,  6,  0,  5,  7 }   /* Byte 7 */
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+	/* Ch 0     1         2         3  */
+	{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 },
+	{ 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }
+	},
+
+	.ect = 1, /* Early Command Training */
+};
+
+const struct mb_lpddr4x_cfg *__weak variant_memory_params(void)
+{
+	return &mem_config;
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c
Gerrit-Change-Number: 39363
Gerrit-PatchSet: 1
Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-MessageType: newchange



    