Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/elog.c 3 files changed, 77 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c..68c33c1 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -51,6 +51,8 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index d962b75..f1d7b65 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += smmrelocate.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += xhci.c
smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 88760b9..c3509df 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> @@ -56,6 +57,77 @@ } }
+static void pch_log_add_elog_event(const struct pme_map *ipme_map) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((ipme_map->devfn == PCH_DEVFN_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(ipme_map->wake_source, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; + bool dev_found = false; + + const struct pme_map ipme_map[] = { + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { SA_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + { SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + { SA_DEVFN_TCSS_DMA0, ELOG_WAKE_SOURCE_PME_TCSS_DMA0 }, + { SA_DEVFN_TCSS_DMA1, ELOG_WAKE_SOURCE_PME_TCSS_DMA1 }, + }; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + pch_log_add_elog_event(&ipme_map[i]); + dev_found = true; + } + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + /* Check Thunderbolt ports */ + if (!dev_found) { + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + } + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -74,9 +146,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
- /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source();
/* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47399
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/elog.c 2 files changed, 87 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/2
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47399
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/elog.c 2 files changed, 86 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/3
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47399
to look at the new patch set (#5).
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/elog.c 2 files changed, 70 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/5
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47399
to look at the new patch set (#6).
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/elog.c 2 files changed, 70 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/6
Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47399/comment/bc307d28_08523f17 PS6, Line 119: ARRAY_SIZE(xhci_wake_info)); nit: seems to fit in 96 characters.
Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Angel Pons, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47399
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/elog.c 2 files changed, 69 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47399/7
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47399/comment/a4e403ef_d7bb6862 PS6, Line 119: ARRAY_SIZE(xhci_wake_info));
nit: seems to fit in 96 characters.
Done
Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
Patch Set 7: Code-Review+2
Attention is currently required from: Tim Wawrzynczak. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
Patch Set 7: Code-Review+2
Attention is currently required from: Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47399 )
Change subject: soc/intel/alderlake: Log internal device wake events ......................................................................
soc/intel/alderlake: Log internal device wake events
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/elog.c 2 files changed, 69 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3bcdb22..19b4db0 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -63,6 +63,8 @@ select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 88bf344..1efba25 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <stdint.h> @@ -56,6 +57,70 @@ } }
+static void pch_log_pme_internal_wake_source(void) +{ + const struct pme_map ipme_map[] = { + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + }; + const struct xhci_wake_info xhci_wake_info[] = { + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { SA_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + }; + bool dev_found = false; + size_t i; + + for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { + const struct device *dev = pcidev_path_on_root(ipme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ipme_map[i].wake_source, 0); + dev_found = true; + } + } + + /* Check Thunderbolt ports */ + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + + /* Check DMA devices */ + for (i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i); + dev_found = true; + } + } + + /* + * Probe the XHCI controllers and their USB2 and USB3 ports to determine + * if any of them were wake sources. + */ + dev_found |= xhci_update_wake_event(xhci_wake_info, ARRAY_SIZE(xhci_wake_info)); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -74,9 +139,9 @@ if (ps->gpe0_sts[GPE_STD] & PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
- /* Internal PME (TODO: determine wake device) */ + /* Internal PME */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source();
/* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)