Change in coreboot[master]: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`

This is needed because a follow-up removes Intel common SoC code Kconfig
options. This will eventually be deduplicated once merged with Haswell.

Tested on out-of-tree Acer E5-573, still boots.

Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/cpu.c
1 file changed, 23 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46731/1

diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 00460c6..694c727 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -290,6 +290,28 @@
    wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }

+static void configure_thermal_target(void)
+{
+	config_t *conf;
+	struct device *lapic;
+	msr_t msr;
+
+	/* Find pointer to CPU configuration */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic || !lapic->chip_info)
+		return;
+	conf = lapic->chip_info;
+
+	/* Set TCC activation offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
 static void configure_misc(void)
 {
    msr_t msr;
@@ -372,7 +394,7 @@
    configure_misc();

/* Thermal throttle activation offset */
-	configure_tcc_thermal_target();
+	configure_thermal_target();

/* Enable Direct Cache Access */
    configure_dca_cap();

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/46731/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46731/1//COMMIT_MSG@7 
PS1, Line 7: Re-add
What commit removed it?

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46731/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46731/1//COMMIT_MSG@7 
PS1, Line 7: Re-add
> What commit removed it?

CB:41855 (will update the commit message later)

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46731

to look at the new patch set (#2).

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`

Commit 360684b (soc/intel/common: add TCC activation functionality) made
Broadwell use common SoC code. However, this makes Broadwell depend on
SoC code, which prevents splitting Broadwell into CPU, northbridge and
southbridge, a stepping stone before merging with Haswell and Lynxpoint.

Tested on out-of-tree Acer E5-573, still boots.

Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/cpu.c
1 file changed, 23 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46731/2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46731/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46731/1//COMMIT_MSG@7 
PS1, Line 7: Re-add
> CB:41855 (will update the commit message later)

Done

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

Patch Set 7: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

Patch Set 7: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/46731/7/src/soc/intel/broadwell/cpu... 
File src/soc/intel/broadwell/cpu.c:

https://review.coreboot.org/c/coreboot/+/46731/7/src/soc/intel/broadwell/cpu... 
PS7, Line 293: d configure_thermal_target(void)
             : {
             : 	config_t *conf;
             : 	struct device *lapic;
             : 	msr_t msr;
             : 
             : 	/* Find pointer to CPU configuration */
             : 	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
             : 	if (!lapic || !lapic->chip_info)
             : 		return;
             : 	conf = lapic->chip_info;
             : 
             : 	/* Set TCC activation offset if supported */
             : 	msr = rdmsr(MSR_PLATFORM_INFO);
             : 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
             : 		msr = rdmsr(MSR_TEMPERATURE_TARGET);
             : 		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
             : 		msr.lo |= (conf->tcc_offset & 0xf) << 24;
             : 		wrmsr(MSR_TEMPERATURE_TARGET, msr);
             : 	}
             : }
should be moved to cpu/common later

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`

Commit 360684b (soc/intel/common: add TCC activation functionality) made
Broadwell use common SoC code. However, this makes Broadwell depend on
SoC code, which prevents splitting Broadwell into CPU, northbridge and
southbridge, a stepping stone before merging with Haswell and Lynxpoint.

Tested on out-of-tree Acer E5-573, still boots.

Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46731
Reviewed-by: Arthur Heymans 
Reviewed-by: Michael Niewöhner 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/cpu.c
1 file changed, 23 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 00460c6..694c727 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -290,6 +290,28 @@
    wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }

+static void configure_thermal_target(void)
+{
+	config_t *conf;
+	struct device *lapic;
+	msr_t msr;
+
+	/* Find pointer to CPU configuration */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic || !lapic->chip_info)
+		return;
+	conf = lapic->chip_info;
+
+	/* Set TCC activation offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
 static void configure_misc(void)
 {
    msr_t msr;
@@ -372,7 +394,7 @@
    configure_misc();

/* Thermal throttle activation offset */
-	configure_tcc_thermal_target();
+	configure_thermal_target();

/* Enable Direct Cache Access */
    configure_dca_cap();