[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_stack_mmios

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81570?usp=email )

Change subject: soc/intel/xeon_sp: Add soc_add_stack_mmios
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Patch Set 1:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81570/comment/3776a576_a24154a5 :
PS1, Line 10: unused IOAT MMIOs (CPM1 and HQM1). These resources are within stack
> How do you read the stack MMIO range? is there a HOB for that?

xSTACK_RES *sr->PciResourceMem64Base/Limit is the portion for PCI device
xSTACK_RES *sr->Mmio64Base/Limit is the total MMIO range

e.g. in CXL domain setting up, non PCI resources are used

if (sr->Mmio64Base < sr->PciResourceMem64Base) {
                res = new_resource(dev, index++);
                res->base = sr->Mmio64Base;
                res->limit = sr->PciResourceMem64Base - 1;
                res->size = res->limit - res->base + 1;
                res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
        }

https://review.coreboot.org/c/coreboot/+/81570/comment/b089a85f_89d3067e :
PS1, Line 10: unused
> what does unused mean? When it decodes MMIO, it's not unused, is it?

in void create_ioat_domains(const union xeon_domain_path path ...), HQM1 and CPM1 MMIO64 will be always reserved, but for SKUs that is not with HQM1 and CPM1, these resources are not assigned to domains, thus forming MTRR segmentation. Will update the commit message.

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/81570/comment/980b072d_f3c40678 :
PS1, Line 135: 	while (from && (from->path.type != DEVICE_PATH_DOMAIN) &&
This check is not correct, will update.