hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
mediatek/mt8183: Allow modifying vdram2 voltage
DRAM DVFS needs to be calibrated with different vdram2 voltages to get correct parameters. A new API is added to allow changing vdram2 voltage.
BUG=b:80501386 BRANCH=none TEST=measure vdram2 voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 99 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/1
diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 6ed654c..9d689b0 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -19,9 +19,18 @@ enum { PMIC_SWCID = 0x000a, PMIC_VM_MODE = 0x004e, + PMIC_TOP_CKPDN_CON0_SET = 0x010e, + PMIC_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_TOP_CKHWEN_CON0_SET = 0x012c, + PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, PMIC_TOP_RST_MISC = 0x014c, PMIC_TOP_RST_MISC_SET = 0x014e, PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, @@ -33,7 +42,9 @@ PMIC_VDRAM1_DBG0 = 0x161e, PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VDRAM2_OP_EN = 0x1b16, PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VDRAM2_ELR_0 = 0x1ec4, };
struct pmic_setting { @@ -51,5 +62,7 @@ void pmic_set_vcore_vol(unsigned int vcore_uv); unsigned int pmic_get_vdram1_vol(void); void pmic_set_vdram1_vol(unsigned int vdram_uv); +unsigned int pmic_get_vdram2_vol(void); +void pmic_set_vdram2_vol(unsigned int vdram2_uv);
#endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 703de81..f389219 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -15,6 +15,7 @@
#include <assert.h> #include <console/console.h> +#include <delay.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> #include <timer.h> @@ -752,6 +753,45 @@ /* [4:4]: RG_SRCVOLTEN_LP_EN */ {0x134, 0x1, 0x1, 4}, }; +static const int vdram2_votrim[] = { + 0, (-1)*10000, (-1)*20000, (-1)*30000, (-1)*40000, (-1)*50000, (-1)*60000, + (-1)*70000, 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, +}; + +static unsigned int pmic_read_efuse(int i) +{ + unsigned int efuse_data = 0; + + /* 1. enable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); + + /* 2. */ + pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); + + /* 3. Set row to read */ + pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); + + /* 4. Toggle RG_OTP_RD_TRIG */ + if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) + pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); + else + pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); + + /* 5. Polling RG_OTP_RD_BUSY = 0 */ + udelay(300); + while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) + ; + /* 6. Read RG_OTP_DOUT_SW */ + udelay(100); + efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + /* 7. disable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); + + return efuse_data; +} + void pmic_set_power_hold(bool enable) { pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); @@ -851,6 +891,52 @@ pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); }
+unsigned int pmic_get_vdram2_vol(void) +{ + unsigned int cali_trim, cali_efuse; + + if (!pwrap_read_field(PMIC_VDRAM2_OP_EN, 0x1, 15)) + return 0; + + cali_efuse = pmic_read_efuse(104) & 0xF; + cali_trim = pwrap_read_field(PMIC_VDRAM2_ELR_0, 0xF, 0); + return (600 * 1000 - vdram2_votrim[cali_efuse] + vdram2_votrim[cali_trim]); +} + +void pmic_set_vdram2_vol(unsigned int vdram2_uv) +{ + int dram2_ori_mv, cali_efuse, cali_offset_mv, cali_trim, target_mv; + + if (vdram2_uv > 680000) { + assert(0); + return; + } if (vdram2_uv < 530000) { + assert(0); + return; + } + + target_mv = vdram2_uv / 1000 / 10; + target_mv = target_mv * 10; + + cali_efuse = pmic_read_efuse(104) & 0xF; + dram2_ori_mv = 600 - vdram2_votrim[cali_efuse] / 1000; + + if (target_mv >= (dram2_ori_mv + 80)) + cali_trim = 8; + else if ((dram2_ori_mv - 70) >= target_mv) + cali_trim = 7; + else { + cali_trim = 0; + cali_offset_mv = 1000 * (target_mv - dram2_ori_mv); + while ((cali_trim < 15) && (vdram2_votrim[cali_trim] != cali_offset_mv)) ++cali_trim; + } + + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + pwrap_write_field(PMIC_VDRAM2_ELR_0, cali_trim, 0xF, 0); + pwrap_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); + udelay(1); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... PS1, Line 913: } if (vdram2_uv < 530000) { trailing statements should be on next line (or did you mean 'else if'?)
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... PS1, Line 931: while ((cali_trim < 15) && (vdram2_votrim[cali_trim] != cali_offset_mv)) ++cali_trim; line over 96 characters
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... PS1, Line 931: while ((cali_trim < 15) && (vdram2_votrim[cali_trim] != cali_offset_mv)) ++cali_trim; trailing statements should be on next line
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35147
to look at the new patch set (#2).
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
mediatek/mt8183: Allow modifying vdram2 voltage
DRAM DVFS needs to be calibrated with different vdram2 voltages to get correct parameters. A new API is added to allow changing vdram2 voltage.
BUG=b:80501386 BRANCH=none TEST=measure vdram2 voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... PS1, Line 913: } if (vdram2_uv < 530000) {
trailing statements should be on next line (or did you mean 'else if'?)
Done
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... PS1, Line 931: while ((cali_trim < 15) && (vdram2_votrim[cali_trim] != cali_offset_mv)) ++cali_trim;
trailing statements should be on next line
Done
https://review.coreboot.org/c/coreboot/+/35147/1/src/soc/mediatek/mt8183/mt6... PS1, Line 931: while ((cali_trim < 15) && (vdram2_votrim[cali_trim] != cali_offset_mv)) ++cali_trim;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/35147/4/src/soc/mediatek/mt8183/mt6... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/4/src/soc/mediatek/mt8183/mt6... PS4, Line 910: if (vdram2_uv > 680000) { : assert(0); : return; : } else if (vdram2_uv < 530000) { : assert(0); : return; : } Why not just assert(vdram2_uv >= 530000 && vdram2_uv <= 680000);
Yu-Ping Wu has uploaded a new patch set (#5) to the change originally created by hsin-hsiung wang. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
mediatek/mt8183: Allow modifying vdram2 voltage
DRAM DVFS needs to be calibrated with different vdram2 voltages to get correct parameters. A new API is added to allow changing vdram2 voltage.
BUG=b:80501386 BRANCH=none TEST=measure vdram2 voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 104 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/5
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35147/4/src/soc/mediatek/mt8183/mt6... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/4/src/soc/mediatek/mt8183/mt6... PS4, Line 910: if (vdram2_uv > 680000) { : assert(0); : return; : } else if (vdram2_uv < 530000) { : assert(0); : return; : }
Why not just […]
Are we going to fix this?
Hello Yu-Ping Wu, Julius Werner, Tristan Hsieh, huayang duan, Hung-Te Lin, Ben Ho, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35147
to look at the new patch set (#11).
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
mediatek/mt8183: Allow modifying vdram2 voltage
DRAM DVFS needs to be calibrated with different vdram2 voltages to get correct parameters. A new API is added to allow changing vdram2 voltage.
BUG=b:80501386 BRANCH=none TEST=measure vdram2 voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/11
hsin-hsiung wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35147/4/src/soc/mediatek/mt8183/mt6... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/4/src/soc/mediatek/mt8183/mt6... PS4, Line 910: if (vdram2_uv > 680000) { : assert(0); : return; : } else if (vdram2_uv < 530000) { : assert(0); : return; : }
Are we going to fix this?
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35147/12/src/soc/mediatek/mt8183/mt... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/12/src/soc/mediatek/mt8183/mt... PS12, Line 758: (-1)*10000, I'm not sure why we have to write in this form - can we do
-10000, -20000, ... ?
Yu-Ping Wu has uploaded a new patch set (#13) to the change originally created by hsin-hsiung wang. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vddq voltage ......................................................................
mediatek/mt8183: Allow modifying vddq voltage
DRAM DVFS needs to be calibrated with different vddq voltages to get correct parameters. A new API is added to allow changing vddq voltage.
BUG=b:80501386 BRANCH=none TEST=measure vddq voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/13
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vddq voltage ......................................................................
Patch Set 13:
(1 comment)
Changes: 1. Rename vdram2 to vddq 2. Add some assert statements
https://review.coreboot.org/c/coreboot/+/35147/12/src/soc/mediatek/mt8183/mt... File src/soc/mediatek/mt8183/mt6358.c:
https://review.coreboot.org/c/coreboot/+/35147/12/src/soc/mediatek/mt8183/mt... PS12, Line 758: (-1)*10000,
I'm not sure why we have to write in this form - can we do […]
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: mediatek/mt8183: Allow modifying vddq voltage ......................................................................
Patch Set 13: Code-Review+2
Yu-Ping Wu has uploaded a new patch set (#15) to the change originally created by hsin-hsiung wang. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: soc/mediatek/mt8183: Allow modifying vddq voltage ......................................................................
soc/mediatek/mt8183: Allow modifying vddq voltage
DRAM DVFS needs to be calibrated with different vddq voltages to get correct parameters. A new API is added to allow changing vddq voltage.
BUG=b:80501386 BRANCH=none TEST=measure vddq voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/15
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: soc/mediatek/mt8183: Allow modifying vddq voltage ......................................................................
Patch Set 15: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35147 )
Change subject: soc/mediatek/mt8183: Allow modifying vddq voltage ......................................................................
soc/mediatek/mt8183: Allow modifying vddq voltage
DRAM DVFS needs to be calibrated with different vddq voltages to get correct parameters. A new API is added to allow changing vddq voltage.
BUG=b:80501386 BRANCH=none TEST=measure vddq voltage with multimeter
Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147 Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 108 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 6ed654c..6b74695 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -19,9 +19,18 @@ enum { PMIC_SWCID = 0x000a, PMIC_VM_MODE = 0x004e, + PMIC_TOP_CKPDN_CON0_SET = 0x010e, + PMIC_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_TOP_CKHWEN_CON0_SET = 0x012c, + PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, PMIC_TOP_RST_MISC = 0x014c, PMIC_TOP_RST_MISC_SET = 0x014e, PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, @@ -33,7 +42,9 @@ PMIC_VDRAM1_DBG0 = 0x161e, PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VDDQ_OP_EN = 0x1b16, PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VDDQ_ELR_0 = 0x1ec4, };
struct pmic_setting { @@ -51,5 +62,7 @@ void pmic_set_vcore_vol(unsigned int vcore_uv); unsigned int pmic_get_vdram1_vol(void); void pmic_set_vdram1_vol(unsigned int vdram_uv); +unsigned int pmic_get_vddq_vol(void); +void pmic_set_vddq_vol(unsigned int vddq_uv);
#endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 9ee27b9..61b1211 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -15,6 +15,7 @@
#include <assert.h> #include <console/console.h> +#include <delay.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> #include <timer.h> @@ -752,6 +753,55 @@ /* [4:4]: RG_SRCVOLTEN_LP_EN */ {0x134, 0x1, 0x1, 4}, }; + +static const int vddq_votrim[] = { + 0, -10000, -20000, -30000, -40000, -50000, -60000, -70000, + 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, +}; + +static unsigned int pmic_read_efuse(int i) +{ + unsigned int efuse_data = 0; + + /* 1. Enable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); + + /* 2. */ + pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); + + /* 3. Set row to read */ + pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); + + /* 4. Toggle RG_OTP_RD_TRIG */ + if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) + pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); + else + pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); + + /* 5. Polling RG_OTP_RD_BUSY = 0 */ + udelay(300); + while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) + ; + + /* 6. Read RG_OTP_DOUT_SW */ + udelay(100); + efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + + /* 7. Disable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); + + return efuse_data; +} + +static int pmic_get_efuse_votrim(void) +{ + const unsigned int cali_efuse = pmic_read_efuse(104) & 0xF; + assert(cali_efuse < sizeof(vddq_votrim)); + return vddq_votrim[cali_efuse]; +} + void pmic_set_power_hold(bool enable) { pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); @@ -847,6 +897,51 @@ pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); }
+unsigned int pmic_get_vddq_vol(void) +{ + int efuse_votrim; + unsigned int cali_trim; + + if (!pwrap_read_field(PMIC_VDDQ_OP_EN, 0x1, 15)) + return 0; + + efuse_votrim = pmic_get_efuse_votrim(); + cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); + assert(cali_trim < sizeof(vddq_votrim)); + return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; +} + +void pmic_set_vddq_vol(unsigned int vddq_uv) +{ + int target_mv, dram2_ori_mv, cali_offset_uv, cali_trim; + + assert(vddq_uv >= 530000); + assert(vddq_uv <= 680000); + + /* Round down to multiple of 10 */ + target_mv = (vddq_uv / 1000) / 10 * 10; + + dram2_ori_mv = 600 - pmic_get_efuse_votrim() / 1000; + cali_offset_uv = 1000 * (target_mv - dram2_ori_mv); + + if (cali_offset_uv >= 80000) + cali_trim = 8; + else if (cali_offset_uv <= -70000) + cali_trim = 7; + else { + cali_trim = 0; + while (cali_trim < sizeof(vddq_votrim) && + vddq_votrim[cali_trim] != cali_offset_uv) + ++cali_trim; + assert(cali_trim < sizeof(vddq_votrim)); + } + + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + pwrap_write_field(PMIC_VDDQ_ELR_0, cali_trim, 0xF, 0); + pwrap_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); + udelay(1); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */
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build bot (Jenkins) (Code Review) -
hsin-hsiung wang (Code Review)
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Hung-Te Lin (Code Review)
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Patrick Georgi (Code Review)
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Yu-Ping Wu (Code Review)