New subject: Change in coreboot[master]: mb/volteer: New variant for EVT reworked with Dauntless

15 Oct 2020

Hello Jes Klinke,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46437
to review the following change.
Change subject: WIP: New Volteer variant for EVT reworked with Dauntless
......................................................................
WIP: New Volteer variant for EVT reworked with Dauntless
For development of the firmware to run on the Dauntless TPM, a number of
Volteer EVT devices are being reworked to replace the H1 chip with probe
wires to connect to an external Dauntless development board.
Some modification to the AP firmware is required, not least because the
Dauntless chip is connected via I2C bus, instead of SPI.  Most of the
Dauntless developers will not otherwise have a Chrome OS chroot.
Because of the above, I thought it would make sense to have a new
variant, for the reworked EVT, which I intend to create with this CL.
I have not figured out, though, how to keep MAINBOARD_HAS_SPI_TPM_CR50
selected in Kconfig for all the existing variants, while instead
selecting MAINBOARD_HAS_I2C_TPM_CR50 for the new variant only.  As far
as I can tell, we do not have separate Kconfig files for each variant.
If someone can help me how to achieve the above, that would be very
helpful.
Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1
Signed-off-by: jbk@chromeos.org
---
M src/mainboard/google/volteer/Kconfig
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
A src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc
A src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c
A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl
A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h
A src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h
A src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc
A src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt
A src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt
A src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb
11 files changed, 569 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46437/1

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index edc9c91..bb29b82 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -23,7 +23,7 @@
    select HAVE_ACPI_TABLES
    select INTEL_LPSS_UART_FOR_CONSOLE
    select MAINBOARD_HAS_CHROMEOS
-	select MAINBOARD_HAS_SPI_TPM_CR50
+	select MAINBOARD_HAS_I2C_TPM_CR50
    select MAINBOARD_HAS_TPM2
    select PCIEXP_HOTPLUG
    select SOC_INTEL_TIGERLAKE
@@ -70,6 +70,14 @@
 config DRIVER_TPM_SPI_BUS
    default 0x1
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x1
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 config MAINBOARD_DIR
    string
    default "google/volteer"
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 330accc..6fa2671 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -277,7 +277,7 @@
    #|                   | before memory is up       |
    #| GSPI1             | Fingerprint MCU           |
    #| I2C0              | Audio                     |
-	#| I2C1              | Touchscreen               |
+	#| I2C1              | Touchscreen, ti50 TPM     |
    #| I2C2              | WLAN, SAR0                |
    #| I2C3              | Camera, SAR1              |
    #| I2C5              | Trackpad                  |
@@ -286,13 +286,14 @@
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
    	.gspi[0] = {
    		.speed_mhz = 1,
-			.early_init = 1,
+			.early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50),
    	},
    	.i2c[0] = {
    		.speed = I2C_SPEED_FAST,
    	},
    	.i2c[1] = {
    		.speed = I2C_SPEED_FAST,
+			.early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50),
    	},
    	.i2c[2] = {
    		.speed = I2C_SPEED_FAST,
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc
new file mode 100644
index 0000000..13269db
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c b/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c
new file mode 100644
index 0000000..fc23983
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/gpio.c
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A7  : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
+	PAD_CFG_GPO(GPP_A7, 1, DEEP),
+	/* A8  : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_A8, 0, DEEP),
+	/* A10 : I2S2_RXD ==> EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_A10, 1, DEEP),
+	/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A18 : DDSP_HPDB ==> HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
+	PAD_NC(GPP_A19, NONE),
+	/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
+	PAD_NC(GPP_A20, NONE),
+	/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+	/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+
+	/* B3  : CPU_GP2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	/* B5  : ISH_I2C0_CVF_SDA */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	/* B6  : ISH_I2C0_CVF_SCL */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	/* B7  : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	/* B8  : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+	/* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C7  : SML1DATA ==> EN_USI_CHARGE */
+	PAD_CFG_GPO(GPP_C7, 1, DEEP),
+	/* C10 : UART0_RTS# ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	/* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
+	PAD_CFG_GPO(GPP_C13, 1, DEEP),
+	/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* C20 : UART2_RXD ==> FPMCU_INT_L */
+	/* APIC interrupt conflict, so used GPI_INT; see b/147500717 */
+	PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+	/* D1  : ISH_GP1 ==> ISH_ACCEL_INT_L */
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+	/* D2  : ISH_GP2 ==> ISH_LID_OPEN */
+	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	/* D3  : ISH_GP3 ==> ISH_ALS_RGB_INT_L */
+	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+	/* D4  : IMGCLKOUT0 ==> FCAM_RST_L */
+	PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+	/* D6  : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_NC(GPP_D16, UP_20K),
+	/* D17 : ISH_GP4 ==> EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	/* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+
+	/* E1  : SPI1_IO2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E2  : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	/* E3  : CPU_GP0 ==> USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	/* E7  : CPU_GP1 ==> USI_INT */
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+	/* E8  : SPI1_CS1# ==> SLP_S0IX */
+	PAD_CFG_GPO(GPP_E8, 0, DEEP),
+	/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+	/* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */
+	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+	/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E17, 1, DEEP),
+
+	/* F6  : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	/* F8  : I2S_MCLK2_INOUT ==> HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
+	/* F12 : GSXDOUT ==> WWAN_RST_ODL */
+	PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+	/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+	PAD_CFG_GPO(GPP_F13, 1, DEEP),
+	/* F14 : GSXDIN ==> SAR0_INT_L */
+	PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE),
+	/* F15 : GSXSRESET# ==> RCAM_RST_L */
+	PAD_CFG_GPO(GPP_F15, 1, DEEP),
+	/* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	/* F17 : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_F17, 1, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+	/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+
+	/* H3  : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H3, 1, DEEP),
+	/* H6  : I2C3_SDA ==> PCH_I2C3_CAM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7  : I2C3_SCL ==> PCH_I2C3_CAM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8  : I2C4_SDA ==> WWAN_WLAN_COEX1 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9  : I2C4_SCL ==> WWAN_WLAN_COEX2 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+	/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H11, 1, DEEP),
+	/* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	/* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+	/* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */
+	PAD_CFG_GPO(GPP_H14, 0, DEEP),
+	/* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */
+	PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+	/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+	/* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
+	/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+	/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
+	PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+
+	/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+	/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+	/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+	/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+	/* S4 : SNDW2_CLK ==> DMIC_CLK1 */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+	/* S5 : SNDW2_DATA ==> DMIC_DATA1 */
+	PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
+	/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+	/* B11 : PMCALERT# ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+	/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+	/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_NC(GPP_D16, UP_20K),
+
+	/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_F11, 1, DEEP),
+	/* F12 : GSXDOUT ==> WWAN_RST_ODL
+	   To meet timing constrains - drive reset low.
+	   Deasserted in ramstage. */
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+
+	/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_H11, 1, DEEP),
+
+	PAD_CFG_NF(GPP_C18, UP_2K, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */
+	PAD_CFG_NF(GPP_C19, UP_2K, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl
new file mode 100644
index 0000000..418f2e0
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/acpi/mipi_camera.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/acpi/mipi_camera.asl>
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h
new file mode 100644
index 0000000..b5fa8c5
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/include/variant/gpio.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Memory configuration board straps */
+/* Copied from baseboard and may need to change for the new variant. */
+#define GPIO_MEM_CONFIG_0	GPP_C12
+#define GPIO_MEM_CONFIG_1	GPP_C15
+#define GPIO_MEM_CONFIG_2	GPP_C14
+#define GPIO_MEM_CONFIG_3	GPP_D15
+
+#endif
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc
new file mode 100644
index 0000000..37e4c22
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += lp4x-spd-3.hex      # ID = 1(0b0001)  Parts = K4UBE3D4AA-MGCL
+SPD_SOURCES += lp4x-spd-4.hex      # ID = 2(0b0010)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += lp4x-spd-2.hex      # ID = 3(0b0011)  Parts = H9HCNNNFAMMLXR-NEE
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt
new file mode 100644
index 0000000..637fd23
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/dram_id.generated.txt
@@ -0,0 +1,6 @@
+DRAM Part Name                 ID to assign
+K4U6E3S4AA-MGCL                0 (0000)
+K4UBE3D4AA-MGCL                1 (0001)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+MT53E1G32D2NP-046 WT:A         2 (0010)
+H9HCNNNFAMMLXR-NEE             3 (0011)
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt
new file mode 100644
index 0000000..c532d0d
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/memory/mem_list_variant.txt
@@ -0,0 +1,5 @@
+K4U6E3S4AA-MGCL
+K4UBE3D4AA-MGCL
+H9HCNNNBKMMLXR-NEE
+MT53E1G32D2NP-046 WT:A
+H9HCNNNFAMMLXR-NEE
diff --git a/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb
new file mode 100644
index 0000000..56ddaf7
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volteer2_ti50/overridetree.cb
@@ -0,0 +1,246 @@
+chip soc/intel/tigerlake
+	register "TcssAuxOri" = "1"
+	register "IomTypeCPortPadCfg[0]" = "0x090E000A"
+	register "IomTypeCPortPadCfg[1]" = "0x090E000D"
+	register "DdiPort1Hpd" = "0"
+	register "DdiPort2Hpd" = "0"
+
+	device domain 0 on
+		device ref dptf on
+			chip drivers/intel/dptf
+				## Active Policy
+				register "policies.active" = "{
+					[0] = {.target = DPTF_CPU,
+					       .thresholds = {TEMP_PCT(85, 90),
+							      TEMP_PCT(80, 69),
+							      TEMP_PCT(75, 56),
+							      TEMP_PCT(70, 46),
+							      TEMP_PCT(65, 36),}},
+					[1] = {.target = DPTF_TEMP_SENSOR_0,
+					       .thresholds = {TEMP_PCT(53, 90),
+							      TEMP_PCT(50, 69),
+							      TEMP_PCT(48, 56),
+							      TEMP_PCT(45, 46),
+							      TEMP_PCT(42, 36),}},
+					[2] = {.target = DPTF_TEMP_SENSOR_1,
+					       .thresholds = {TEMP_PCT(50, 90),
+							      TEMP_PCT(47, 69),
+							      TEMP_PCT(45, 56),
+							      TEMP_PCT(42, 46),
+							      TEMP_PCT(39, 36),}},
+					[3] = {.target = DPTF_TEMP_SENSOR_2,
+					       .thresholds = {TEMP_PCT(53, 90),
+							      TEMP_PCT(50, 69),
+							      TEMP_PCT(48, 56),
+							      TEMP_PCT(45, 46),
+							      TEMP_PCT(42, 36),}},
+					[4] = {.target = DPTF_TEMP_SENSOR_3,
+					       .thresholds = {TEMP_PCT(53, 90),
+							      TEMP_PCT(50, 69),
+							      TEMP_PCT(48, 56),
+							      TEMP_PCT(45, 46),
+							      TEMP_PCT(42, 36),}}}"
+				device generic 0 on end
+			end
+		end # DPTF				0x9A03
+		device ref ipu on end # IPU                           0x9A19
+		device ref i2c0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+					probe AUDIO MAX98357_ALC5682I_I2S
+					probe AUDIO MAX98373_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "0"
+				register "imon_slot_no" = "1"
+				register "uid" = "0"
+				register "desc" = ""Right Speaker Amp""
+				register "name" = ""MAXR""
+				device i2c 31 on
+					probe AUDIO MAX98373_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "2"
+				register "imon_slot_no" = "3"
+				register "uid" = "1"
+				register "desc" = ""Left Speaker Amp""
+				register "name" = ""MAXL""
+				device i2c 32 on
+					probe AUDIO MAX98373_ALC5682I_I2S
+				end
+			end
+			chip drivers/i2c/tpm
+				register "hid" = ""GOOG0005""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
+				device i2c 50 on end
+			end
+		end
+		device ref i2c1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				# Parameter T3 >= 10ms
+				register "generic.reset_delay_ms" = "120"
+				# Parameter T2 >= 1ms
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				# Parameter T1 >= 10ms
+				register "generic.enable_delay_ms" = "12"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)"
+				# Parameter T4 >= 1ms
+				register "generic.stop_off_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 14 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN90FC""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on end
+			end
+			chip drivers/generic/gpio_keys
+				register "name" = ""PENH""
+				# GPP_B3 is the IRQ source, and GPP_E1 is the wake source
+				register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)"
+				register "key.wake_gpe" = "GPE0_DW2_01"
+				register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
+				register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
+				register "key.dev_name" = ""EJCT""
+				register "key.linux_code" = "SW_PEN_INSERTED"
+				register "key.linux_input_type" = "EV_SW"
+				register "key.label" = ""pen_eject""
+				device generic 0 on end
+			end
+		end
+		device ref i2c2 on
+			chip drivers/i2c/sx9310
+				register "desc" = ""SAR0 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "0"
+				register "reg_prox_ctrl0" = "0x10"
+				register "reg_prox_ctrl1" = "0x00"
+				register "reg_prox_ctrl2" = "0x84"
+				register "reg_prox_ctrl3" = "0x0e"
+				register "reg_prox_ctrl4" = "0x07"
+				register "reg_prox_ctrl5" = "0xc6"
+				register "reg_prox_ctrl6" = "0x20"
+				register "reg_prox_ctrl7" = "0x0d"
+				register "reg_prox_ctrl8" = "0x8d"
+				register "reg_prox_ctrl9" = "0x43"
+				register "reg_prox_ctrl10" = "0x1f"
+				register "reg_prox_ctrl11" = "0x00"
+				register "reg_prox_ctrl12" = "0x00"
+				register "reg_prox_ctrl13" = "0x00"
+				register "reg_prox_ctrl14" = "0x00"
+				register "reg_prox_ctrl15" = "0x00"
+				register "reg_prox_ctrl16" = "0x00"
+				register "reg_prox_ctrl17" = "0x00"
+				register "reg_prox_ctrl18" = "0x00"
+				register "reg_prox_ctrl19" = "0x00"
+				register "reg_sar_ctrl0" = "0x50"
+				register "reg_sar_ctrl1" = "0x8a"
+				register "reg_sar_ctrl2" = "0x3c"
+				device i2c 28 on end
+			end
+		end
+		device ref i2c5 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end
+		device ref hda on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98357A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
+				register "sdmode_delay" = "5"
+				device generic 0 on
+					probe AUDIO MAX98357_ALC5682I_I2S
+				end
+			end
+			chip drivers/intel/soundwire
+				device generic 0 on
+					probe AUDIO MAX98373_ALC5682_SNDW
+					chip drivers/soundwire/alc5682
+						# SoundWire Link 0 ID 1
+						register "desc" = ""Headset Codec""
+						device generic 0.1 on end
+					end
+					chip drivers/soundwire/max98373
+						# SoundWire Link 1 ID 3
+						register "desc" = ""Left Speaker Amp""
+						device generic 1.3 on end
+					end
+					chip drivers/soundwire/max98373
+						# SoundWire Link 1 ID 7
+						register "desc" = ""Right Speaker Amp""
+						device generic 1.7 on end
+					end
+				end
+			end
+		end
+		device ref pmc hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "9"
+						register "usb3_port_number" = "1"
+						# SBU & HSL follow CC
+						device generic 0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "4"
+						register "usb3_port_number" = "2"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 on
+							probe DB_USB USB4_GEN2
+							probe DB_USB USB3_ACTIVE
+							probe DB_USB USB4_GEN3
+							probe DB_USB USB3_NO_A
+						end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "4"
+						register "usb3_port_number" = "2"
+						# SBU & HSL follow CC
+						device generic 1 on
+							probe DB_USB USB3_PASSIVE
+						end
+					end
+				end
+			end
+		end
+	end
+end
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1
Gerrit-Change-Number: 46437
Gerrit-PatchSet: 1
Gerrit-Owner: Jes Klinke jbk@chromium.org
Gerrit-Reviewer: Jes Klinke jbk@google.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: WIP: New Volteer variant for EVT reworked with Dauntless