[XS] Change in coreboot[main]: soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR en... - coreboot-gerrit

27 Sep 2023


      Attention is currently required from: Krishna P Bhat D, Rizwan Qureshi.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78055?usp=email )
Change subject: soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabled
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Patch Set 4: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7c9bf8b8606cf68ec798ff35129e92cd60bbb137
Gerrit-Change-Number: 78055
Gerrit-PatchSet: 4
Gerrit-Owner: Krishna P Bhat D krishna.p.bhat.d@intel.com
Gerrit-Reviewer: Anil Kumar K anil.kumar.k@intel.com
Gerrit-Reviewer: Rizwan Qureshi rizwan.qureshi@intel.com
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Gerrit-Attention: Rizwan Qureshi rizwan.qureshi@intel.com
Gerrit-Attention: Krishna P Bhat D krishna.p.bhat.d@intel.com
Gerrit-Comment-Date: Wed, 27 Sep 2023 19:49:13 +0000
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