Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39050 )
Change subject: cpi/xeonsp: Cache SPI region ......................................................................
cpi/xeonsp: Cache SPI region
Instead of trying to hardcode caching parameters for FSP-T, use common code to cache BIOS region. This seems to be an undocumented requirement for FSP-M to function correctly.
Change-Id: I926722ecd7237bea236a4906b899a51e4963f740 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/spi.c 4 files changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/39050/1
diff --git a/src/cpu/intel/xeonsp/Kconfig b/src/cpu/intel/xeonsp/Kconfig index 1a7d8bc..3fa1d5a 100644 --- a/src/cpu/intel/xeonsp/Kconfig +++ b/src/cpu/intel/xeonsp/Kconfig @@ -29,6 +29,8 @@ select DISPLAY_MTRRS select FSP_M_XIP select INTEL_DESCRIPTOR_MODE_CAPABLE + select SPI_FLASH + select SOC_INTEL_COMMON_BLOCK_FAST_SPI
if CPU_INTEL_MODEL_XEONSP config MMCONF_BASE_ADDRESS diff --git a/src/cpu/intel/xeonsp/Makefile.inc b/src/cpu/intel/xeonsp/Makefile.inc index af1bb72..8e20a14 100644 --- a/src/cpu/intel/xeonsp/Makefile.inc +++ b/src/cpu/intel/xeonsp/Makefile.inc @@ -18,9 +18,9 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm
-bootblock-y += bootblock.c -romstage-y += ../../../cpu/intel/car/romstage.c -romstage-y += postcar.c romstage.c -ramstage-y += model_xeonsp_init.c lpc.c ramstage.c +bootblock-y += bootblock.c spi.c +romstage-y += ../../../cpu/intel/car/romstage.c spi.c +romstage-y += postcar.c romstage.c spi.c +ramstage-y += model_xeonsp_init.c lpc.c ramstage.c spi.c
CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include diff --git a/src/cpu/intel/xeonsp/bootblock.c b/src/cpu/intel/xeonsp/bootblock.c index f3ffe66..6c3a367 100644 --- a/src/cpu/intel/xeonsp/bootblock.c +++ b/src/cpu/intel/xeonsp/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <FsptUpd.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> #include <soc/pci_devs.h> @@ -44,6 +45,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + fast_spi_cache_bios_region(); + /* set up P2SB BAR */ uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd|PCI_COMMAND_MEMORY); diff --git a/src/cpu/intel/xeonsp/spi.c b/src/cpu/intel/xeonsp/spi.c new file mode 100644 index 0000000..5bc4da5 --- /dev/null +++ b/src/cpu/intel/xeonsp/spi.c @@ -0,0 +1,8 @@ +#include <spi-generic.h> +#include <intelblocks/fast_spi.h> + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 } + }; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39050
to look at the new patch set (#2).
Change subject: cpu/intel/xeonsp: Cache BIOS SPI region ......................................................................
cpu/intel/xeonsp: Cache BIOS SPI region
Instead of trying to hardcode caching parameters for FSP-T, use common code to cache BIOS region. This seems to be an undocumented requirement for FSP-M to function correctly.
Change-Id: I926722ecd7237bea236a4906b899a51e4963f740 Signed-off-by: Andrey Petrov anpetrov@fb.com --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/spi.c 4 files changed, 32 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/39050/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39050 )
Change subject: cpu/intel/xeonsp: Cache BIOS SPI region ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39050/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39050/2//COMMIT_MSG@10 PS2, Line 10: This seems to be an undocumented requirement : for FSP-M to function correctly. AFAIK, it is a documented requirement of the MRC (Memory Reference Code).
I think FSP-M also does QPI/UPI init. Performing any flash accesses while initializing QPI does not seem to be a good idea.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39050 )
Change subject: cpu/intel/xeonsp: Cache BIOS SPI region ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39050/2/src/cpu/intel/xeonsp/spi.c File src/cpu/intel/xeonsp/spi.c:
https://review.coreboot.org/c/coreboot/+/39050/2/src/cpu/intel/xeonsp/spi.c@... PS2, Line 21: }; one less indent here
Andrey Petrov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39050 )
Change subject: cpu/intel/xeonsp: Cache BIOS SPI region ......................................................................
Abandoned
killing in favor of new patchset
-
Aaron Durbin (Code Review) -
Andrey Petrov (Code Review)
-
Angel Pons (Code Review)