Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
mb/google/puff/var/dooly: Update DPTF parameters
DPTF paramerters form thermal team. Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010 BRANCH=puff TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Signed-off-by: Tony Huang tony-huang@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 23 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48206/1
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index efa7d71..45c43cc 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/cannonlake
+ register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 49, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1"
@@ -176,47 +181,36 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(90, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(75, 60), + TEMP_PCT(65, 50), + TEMP_PCT(45, 40), + TEMP_PCT(30, 30),}}"
## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 70, 60000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 76, 60000)"
## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-25W PL1 in 1000mW increments, avg over 28-32s interval + # 40-49W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .max_power = 25000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.power_limits.pl2" = "{ + .min_power = 40000, + .max_power = 49000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}"
## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1: Code-Review+2
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/dooly/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... PS1, Line 209: 40000 Keep both PL2 Max and Min value same as 49W.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1: Code-Review+2
Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/dooly/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... PS1, Line 209: 40000
Keep both PL2 Max and Min value same as 49W.
I see other puff series set PL2 15/51 or 25/64. May I know why this suggestion?
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/dooly/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... PS1, Line 209: 40000
I see other puff series set PL2 15/51 or 25/64. […]
DPTF does not throttle PL2, so any minimum value here does not impact the existing behavior on the system. But we suggest to keep the same values for PL2 Max and Min.
Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/dooly/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... PS1, Line 209: 40000
DPTF does not throttle PL2, so any minimum value here does not impact the existing behavior on the s […]
Got it. Thanks for the explanation. Since we are close to a build, we will consider implement this at next stage.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/dooly/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/48206/1/src/mainboard/google/hatch/... PS1, Line 209: 40000
Got it. Thanks for the explanation. […]
ok
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48206 )
Change subject: mb/google/puff/var/dooly: Update DPTF parameters ......................................................................
mb/google/puff/var/dooly: Update DPTF parameters
DPTF paramerters form thermal team. Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010 BRANCH=puff TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Signed-off-by: Tony Huang tony-huang@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Sam McNally sammc@google.com Reviewed-by: Edward O'Callaghan quasisec@chromium.org Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 23 insertions(+), 29 deletions(-)
Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Sam McNally: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index efa7d71..45c43cc 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/cannonlake
+ register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 49, + }" + # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1"
@@ -176,47 +181,36 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(90, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(75, 60), + TEMP_PCT(65, 50), + TEMP_PCT(45, 40), + TEMP_PCT(30, 30),}}"
## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 70, 60000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 76, 60000)"
## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control - # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-25W PL1 in 1000mW increments, avg over 28-32s interval + # 40-49W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .max_power = 25000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf[0]" = "{ 255, 1700 }" - register "controls.charger_perf[1]" = "{ 24, 1500 }" - register "controls.charger_perf[2]" = "{ 16, 1000 }" - register "controls.charger_perf[3]" = "{ 8, 500 }" + register "controls.power_limits.pl2" = "{ + .min_power = 40000, + .max_power = 49000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}"
## Fan Performance Control (Percent, Speed, Noise, Power) register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
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Edward O'Callaghan (Code Review) -
Patrick Georgi (Code Review)
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Sam McNally (Code Review)
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Sumeet R Pawnikar (Code Review)
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Tony Huang (Code Review)