Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 )
Change subject: soc/intel/xeon_sp: Enable SMI handler ......................................................................
Patch Set 13:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/block... File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/common/block... PS13, Line 271: pmc_clear_tco_status is there a need for preprocessor directives?
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/cpx/... File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/cpx/... PS13, Line 176: * TODO: Now that all APs have been relocated as well as the BSP let SMIs remove TODO
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/incl... PS13, Line 14: u8 uior; you need to sync the ACPI GNVS against this struct
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/skx/... File src/soc/intel/xeon_sp/skx/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/skx/... PS13, Line 12: subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm duplicate entry
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/46231/13/src/soc/intel/xeon_sp/unco... PS13, Line 293: uintptr_t tseg_base = pci_s_read_config32(PCI_DEV(0, use get_tseg_base_lim instead
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Patrick Rudolph (Code Review)