EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefit acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 40 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/1
diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 9686ddc..ab76418 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -2,6 +2,8 @@
#include <soc/iomap.h>
+#define PAD_CFG0_TX_STATE 0x400000 + /* Get pin control MMIO address */ Method (GPAD, 0x1) { @@ -117,3 +119,31 @@ /* Arg1 - Value for control register */ GPSB (Arg0, 3, Arg1) } + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GPAD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 |= PAD_CFG0_TX_STATE +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GPAD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 &= ~PAD_CFG0_TX_STATE +} diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 17940e9..63ba26c 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -474,45 +474,6 @@ return 0; }
-static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - /* Store (0x40, Local0) */ - acpigen_write_store(); - acpigen_write_integer(GPIO_PIN_OUT); - acpigen_emit_byte(LOCAL0_OP); - - acpigen_soc_get_gpio_in_local5(addr); - - if (val) { - /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); - } else { - /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(LOCAL0_OP, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * SB.GPW2 (addr, Local5) - * _SB.GPW2 is used to write control byte in control register - * / byte 2. It is defined in gpio_lib.asl. - */ - acpigen_emit_namestring("\_SB.GPW2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - - return 0; -} - int acpigen_soc_read_rx_gpio(unsigned int gpio_num) { return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); @@ -523,12 +484,20 @@ return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); }
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + int acpigen_soc_set_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_set_gpio_val(gpio_num, 1); + return acpigen_soc_gpio_op("\_SB.STXS", gpio_num); }
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_set_gpio_val(gpio_num, 0); + return acpigen_soc_gpio_op("\_SB.CTXS", gpio_num); }
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 1:
I plan to rewrite acpi.c by replace gpiolib method :)
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Chris Wang, Kyösti Mälkki, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48943
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefit acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 41 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/2
EricR Lai has removed Chris Wang from this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Removed reviewer Chris Wang.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 2:
@AMD, please help review this, I want we can use this in cezanne for guybrush project :)
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 2:
(2 comments)
Patch Set 2:
@AMD, please help review this, I want we can use this in cezanne for guybrush project :)
returned from vacation today and had a brief look. did you test the change on all platforms it might affect?
https://review.coreboot.org/c/coreboot/+/48943/2/src/soc/amd/common/acpi/gpi... File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/2/src/soc/amd/common/acpi/gpi... PS2, Line 125: Tx i'd say that "output" would be much clearer than "tx" here
https://review.coreboot.org/c/coreboot/+/48943/2/src/soc/amd/common/acpi/gpi... PS2, Line 139: Tx same
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 2:
Patch Set 2:
(2 comments)
Patch Set 2:
@AMD, please help review this, I want we can use this in cezanne for guybrush project :)
returned from vacation today and had a brief look. did you test the change on all platforms it might affect?
I only have Vilboz on my hand, and I think this is common for all platform. I verified on Vilboz and work as expected. I checked the acpi table and touch function.
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Mathew King, Tim Wawrzynczak, Kyösti Mälkki, chris wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48943
to look at the new patch set (#3).
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefit acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 41 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48943/2/src/soc/amd/common/acpi/gpi... File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/2/src/soc/amd/common/acpi/gpi... PS2, Line 125: Tx
i'd say that "output" would be much clearer than "tx" here
Done
https://review.coreboot.org/c/coreboot/+/48943/2/src/soc/amd/common/acpi/gpi... PS2, Line 139: Tx
same
Done
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Mathew King, Tim Wawrzynczak, Kyösti Mälkki, chris wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48943
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefit acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 41 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 4: Code-Review+1
I like making this sort of thing common 😊
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 4: Code-Review+2
I only have Vilboz on my hand, and I think this is common for all platform. I verified on Vilboz and work as expected. I checked the acpi table and touch function.
since the patch only affects amd/picasso and it worked as expected on a machine that uses that mechanism, that should be sufficient. aligning different platforms if they are similar enough is something i like
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/4/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/48943/4/src/soc/amd/picasso/acpi.c@... PS4, Line 489: { i wonder if it would be useful to keep the check if gpio_num is lower than SOC_GPIO_TOTAL_PINS in the new code to avoid clobbering some unrelated registers if gpio_num is way too large
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/4/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/48943/4/src/soc/amd/picasso/acpi.c@... PS4, Line 489: {
i wonder if it would be useful to keep the check if gpio_num is lower than SOC_GPIO_TOTAL_PINS in th […]
SG!
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/4/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/48943/4/src/soc/amd/picasso/acpi.c@... PS4, Line 489: {
SG!
Done
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Mathew King, Tim Wawrzynczak, Kyösti Mälkki, chris wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48943
to look at the new patch set (#5).
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefit acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 46 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/5
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 5: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48943/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48943/5//COMMIT_MSG@9 PS5, Line 9: Intel ACPI method Could that be shared?
https://review.coreboot.org/c/coreboot/+/48943/5//COMMIT_MSG@10 PS5, Line 10: benefit benefits
Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Mathew King, Tim Wawrzynczak, Kyösti Mälkki, chris wang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48943
to look at the new patch set (#6).
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 46 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/6
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48943/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48943/5//COMMIT_MSG@9 PS5, Line 9: Intel ACPI method
Could that be shared?
No but for better programing by developer. You can understand it is the same usage at first time :)
https://review.coreboot.org/c/coreboot/+/48943/5//COMMIT_MSG@10 PS5, Line 10: benefit
benefits
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... PS6, Line 5: #define GPIO_OUTPUT_SHIFT 22 : #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) These are already defined in gpio_banks.h. Why not include that directly instead of re-defining this?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... PS6, Line 5: #define GPIO_OUTPUT_SHIFT 22 : #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
These are already defined in gpio_banks.h. […]
Too many type conflict when I include that file...
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... PS6, Line 5: #define GPIO_OUTPUT_SHIFT 22 : #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
Too many type conflict when I include that file...
Aah. I think what we need is basically reorganizing gpio_banks.h so that the #defines are at the top and rest of the structure and function declarations at bottom guarded by #ifndef __ACPI__.
Anyways, we can go ahead with this, but we should really get rid of the duplicate definitions.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/6/src/soc/amd/common/acpi/gpi... PS6, Line 5: #define GPIO_OUTPUT_SHIFT 22 : #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
Aah. I think what we need is basically reorganizing gpio_banks. […]
I agree! I can try it later. Maybe you can fill an issue in the guybrush to me 😊
Attention is currently required from: EricR Lai. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/acpi/gpio_bank_lib.asl:
https://review.coreboot.org/c/coreboot/+/48943/comment/6425f370_a2a8a42b PS6, Line 5: #define GPIO_OUTPUT_SHIFT 22 : #define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT)
I agree! I can try it later. […]
i'm ok with doing this as a follow-up
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48943 )
Change subject: soc/amd/picasso: Add STXS and CTXS method ......................................................................
soc/amd/picasso: Add STXS and CTXS method
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943 Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/picasso/acpi.c 2 files changed, 46 insertions(+), 41 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index 9686ddc..f209f44 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -2,6 +2,9 @@
#include <soc/iomap.h>
+#define GPIO_OUTPUT_SHIFT 22 +#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) + /* Get pin control MMIO address */ Method (GPAD, 0x1) { @@ -117,3 +120,31 @@ /* Arg1 - Value for control register */ GPSB (Arg0, 3, Arg1) } + +/* + * Set GPIO Output Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 |= GPIO_OUTPUT_VALUE +} + +/* + * Clear GPIO Output Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4) + Field (GPDW, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 &= ~GPIO_OUTPUT_VALUE +} diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index f5f1113..445815a 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -475,45 +475,6 @@ return 0; }
-static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - uintptr_t addr = gpio_get_address(gpio_num); - - /* Store (0x40, Local0) */ - acpigen_write_store(); - acpigen_write_integer(GPIO_PIN_OUT); - acpigen_emit_byte(LOCAL0_OP); - - acpigen_soc_get_gpio_in_local5(addr); - - if (val) { - /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); - } else { - /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(LOCAL0_OP, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * SB.GPW2 (addr, Local5) - * _SB.GPW2 is used to write control byte in control register - * / byte 2. It is defined in gpio_lib.asl. - */ - acpigen_emit_namestring("\_SB.GPW2"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - - return 0; -} - int acpigen_soc_read_rx_gpio(unsigned int gpio_num) { return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); @@ -524,12 +485,25 @@ return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); }
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + int acpigen_soc_set_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_set_gpio_val(gpio_num, 1); + return acpigen_soc_gpio_op("\_SB.STXS", gpio_num); }
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) { - return acpigen_soc_set_gpio_val(gpio_num, 0); + return acpigen_soc_gpio_op("\_SB.CTXS", gpio_num); }
-
EricR Lai (Code Review) -
Felix Held (Code Review)
-
Furquan Shaikh (Code Review)
-
Paul Menzel (Code Review)
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Tim Wawrzynczak (Code Review)