Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31375 )

Change subject: soc/intel/cannonlake: Configure serial debug uart
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soc/intel/cannonlake: Configure serial debug uart

Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE
SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose
The default value of SerialIoDebugUartNumber is 2 by default it selects UART 2
so it needs to be initialized as per board config

BUG=b:123702398

Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525
Signed-off-by: Ronak Kanabar 
Reviewed-on: https://review.coreboot.org/c/31375
Reviewed-by: Furquan Shaikh 
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Rizwan Qureshi: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 866d9c8..c276c86 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -163,6 +163,9 @@
    	dev->enabled = 0;
    params->XdciEnable = dev->enabled;

+	/* Set Debug serial port */
+	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+
    /* Enable CNVi Wifi if enabled in device tree */
    dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
    params->PchCnviMode = dev->enabled;