Change in coreboot[master]: soc/intel/alderlake: Update CPU IDs with correct steppings

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63299 )

Change subject: soc/intel/alderlake: Update CPU IDs with correct steppings
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soc/intel/alderlake: Update CPU IDs with correct steppings

Update ADL CPU IDs per correct steppings and add new CPU ID
0x906A3 (L0 stepping).

Signed-off-by: Lean Sheng Tan 
Change-Id: I722043c493b8c3de8965bcaa13f33c907d51f284
---
M src/include/cpu/intel/cpu_ids.h
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/common/block/cpu/mp_init.c
3 files changed, 15 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63299/1

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 07e359a..6d36851 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -51,10 +51,11 @@
 #define CPUID_ELKHARTLAKE_A0		0x90660
 #define CPUID_ELKHARTLAKE_B0		0x90661
 #define CPUID_ALDERLAKE_S_A0		0x90670
-#define CPUID_ALDERLAKE_A0		0x906a0
-#define CPUID_ALDERLAKE_A1		0x906a1
-#define CPUID_ALDERLAKE_A2		0x906a2
-#define CPUID_ALDERLAKE_A3		0x906a4
+#define CPUID_ALDERLAKE_J0		0x906a0
+#define CPUID_ALDERLAKE_Q0		0x906a1
+#define CPUID_ALDERLAKE_K0		0x906a2
+#define CPUID_ALDERLAKE_L0		0x906a3
+#define CPUID_ALDERLAKE_R0		0x906a4
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index 3342e4b..bdce2b7 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -23,10 +23,11 @@
    u32 cpuid;
    const char *name;
 } cpu_table[] = {
-	{ CPUID_ALDERLAKE_A0, "Alderlake Platform" },
-	{ CPUID_ALDERLAKE_A1, "Alderlake Platform" },
-	{ CPUID_ALDERLAKE_A2, "Alderlake Platform" },
-	{ CPUID_ALDERLAKE_A3, "Alderlake Platform" },
+	{ CPUID_ALDERLAKE_J0, "Alderlake J0 Platform" },
+	{ CPUID_ALDERLAKE_K0, "Alderlake K0 Platform" },
+	{ CPUID_ALDERLAKE_L0, "Alderlake L0 Platform" },
+	{ CPUID_ALDERLAKE_Q0, "Alderlake Q0 Platform" },
+	{ CPUID_ALDERLAKE_R0, "Alderlake R0 Platform" },
    { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" },
 };

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 2d838c5..823f23e 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -70,10 +70,11 @@
    { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 },
    { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 },
-	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0 },
-	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 },
-	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 },
-	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 },
+	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 },
    { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 },
    { 0, 0 },
 };