[XS] Change in coreboot[main]: soc/intel/common/pmc: Fix duplicate GPE DW register check

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86173?usp=email )

Change subject: soc/intel/common/pmc: Fix duplicate GPE DW register check
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soc/intel/common/pmc: Fix duplicate GPE DW register check

The `pmc_gpe_init` function's check for duplicate GPE DW register values
was incomplete. It only checked for duplicates between DW0 and DW1, and
DW1 and DW2, but failed to check if DW0 and DW2 were the same.

This could lead to incorrect GPE routing if DW0 and DW2 happened to have
the same value, even if DW1 was different.

This commit corrects the check to ensure that all three DW registers
(DW0, DW1, and DW2) are compared against each other. If any two
registers have the same value, a message is printed indicating that
the default GPE route will be used.

Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/pmc/pmclib.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/86173/1

diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 0fadd6e..18a527a 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -656,7 +656,7 @@
     * Route the GPIOs to the GPE0 block. Determine that all values
     * are different, and if they aren't use the reset values.
     */
-	if (dw0 == dw1 || dw1 == dw2) {
+	if (dw0 == dw1 || dw1 == dw2 || dw0 == dw2) {
    	printk(BIOS_INFO, "PMC: Using default GPE route.\n");
    	gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG);