Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33435
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for WHLRVP.
BUG=none TEST= Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P usha.p@intel.com Signed-off-by: sridhar sridhar.siricilla@intel.com Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912 --- M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33435/1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index e30da3a..727b009 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1"
+ # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33435 )
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/33435/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33435/1//COMMIT_MSG@12 PS1, Line 12: remove whitespace?
https://review.coreboot.org/#/c/33435/1//COMMIT_MSG@13 PS1, Line 13: same
https://review.coreboot.org/#/c/33435/1/src/mainboard/intel/coffeelake_rvp/v... File src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb:
https://review.coreboot.org/#/c/33435/1/src/mainboard/intel/coffeelake_rvp/v... PS1, Line 14: B/C comment only says DDI ports over B and C is enable bt below code sets it for D and F as well?
https://review.coreboot.org/#/c/33435/1/src/mainboard/intel/coffeelake_rvp/v... PS1, Line 19: B/C same?
Hello Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33435
to look at the new patch set (#2).
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for WHLRVP.
BUG=none TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P usha.p@intel.com Signed-off-by: sridhar sridhar.siricilla@intel.com Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912 --- M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33435/2
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33435 )
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
Patch Set 2:
Patch Set 1:
(4 comments)
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33435 )
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
Patch Set 2: Code-Review+2
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33435 )
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
Patch Set 2: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33435 )
Change subject: mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp ......................................................................
mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for WHLRVP.
BUG=none TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P usha.p@intel.com Signed-off-by: sridhar sridhar.siricilla@intel.com Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435 Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 1 file changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index e30da3a..429d5da 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1"
+ # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C/D/F + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C/D/F + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"