Change in coreboot[master]: nb/intel/gm45: Allow for PCI BARs above 4G

[Nico Huber (Code Review)]

Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64094 )

Change subject: nb/intel/gm45: Allow for PCI BARs above 4G
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Patch Set 3:

(1 comment)

File src/northbridge/intel/gm45/northbridge.c:

https://review.coreboot.org/c/coreboot/+/64094/comment/b8c4d87e_60459e7e 
PS3, Line 189: 	const uint64_t touud = get_touud();
> Even without the reclaiming of memory below 4G, the hardware doesn't map the ME stolen memory for th […]

My concern was more what happens when the ME tries to access its memory
(in case that is mapped 1:1). Technically, its request would pass buses
where another device could positively decode the addresses.

Any UMA device could have that issue, in theory. But GFX, for instance,
is integrated much closer to the DRAM controller. I guess it doesn't
pass any PCI bus.