Attention is currently required from: Subrata Banik, Werner Zeh.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73310 )
Change subject: device/pciexp_device.c: Do not enable common clock if already active ......................................................................
Patch Set 1:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73310/comment/20747fc8_5b1e16ab PS1, Line 11: re-train I would have thought it’s re-training.
https://review.coreboot.org/c/coreboot/+/73310/comment/0ff43e8c_745ceb55 PS1, Line 14: FSP code Which version?
https://review.coreboot.org/c/coreboot/+/73310/comment/760f0ef4_f581f489 PS1, Line 18: re-train Ditto.
https://review.coreboot.org/c/coreboot/+/73310/comment/0c562b60_6d7dfca6 PS1, Line 26: In particular, link issues were discovered : with a Pericom PCIe switch (PI7C9X2G608) on mc_ehl1 where the link has : stalled for a while after the second re-train. Out of curiosity, are two re-trainings spec-compliant, so this is actually a bug of the Pericom PCIe switch?
https://review.coreboot.org/c/coreboot/+/73310/comment/38ad74b5_65a36a93 PS1, Line 33: and thus execution time How much?
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/73310/comment/251757b0_bd9d3ffe PS1, Line 205: printk(BIOS_INFO, "Common Clock Configuration already enabled\n"); Maybe:
PCIe: Common Clock Configuration already enabled, so skip it