[M] Change in coreboot[master]: soc/amd: Create AMD common reset code

[Martin L Roth (Code Review)]

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72658 )

Change subject: soc/amd: Create AMD common reset code
......................................................................

soc/amd: Create AMD common reset code

This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda.
PCO supports the warm reset, and future chips can support it by setting
the SOC_SUPPORTS_WARM_RESET option.

Signed-off-by: Martin Roth 
Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7
---
M src/soc/amd/common/block/include/amdblocks/reset.h
A src/soc/amd/common/block/reset/Kconfig
A src/soc/amd/common/block/reset/Makefile.inc
A src/soc/amd/common/block/reset/reset.c
4 files changed, 73 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/72658/1

diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h
index 353720c..cf002ad 100644
--- a/src/soc/amd/common/block/include/amdblocks/reset.h
+++ b/src/soc/amd/common/block/include/amdblocks/reset.h
@@ -3,9 +3,12 @@
 #ifndef AMD_BLOCK_RESET_H
 #define AMD_BLOCK_RESET_H

-#include <console/console.h>
+#include <amdblocks/acpimmio.h>
 #include <arch/cache.h>
+#include <console/console.h>
 #include <halt.h>
+#include <soc/southbridge.h>
+

void do_warm_reset(void);
 void do_cold_reset(void);
@@ -28,4 +31,10 @@
    halt();
 }

+static inline void set_cf9_reset_to_cold(void)
+{
+	/* De-assert and then assert all PwrGood signals on CF9 reset. */
+	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
+}
+
 #endif /* AMD_BLOCK_RESET_H */
diff --git a/src/soc/amd/common/block/reset/Kconfig b/src/soc/amd/common/block/reset/Kconfig
new file mode 100644
index 0000000..ffb7ee7
--- /dev/null
+++ b/src/soc/amd/common/block/reset/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SOC_AMD_COMMON_BLOCK_RESET
+	bool
+	help
+	  Select this option to use AMD common reset driver support.
+
+config SOC_SUPPORTS_WARM_RESET
+	bool
+	help
+	  Select this option if the chip supports warm reset.
diff --git a/src/soc/amd/common/block/reset/Makefile.inc b/src/soc/amd/common/block/reset/Makefile.inc
new file mode 100644
index 0000000..c53d58b
--- /dev/null
+++ b/src/soc/amd/common/block/reset/Makefile.inc
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_RESET),y)
+
+bootblock-y	+= reset.c
+verstage_x86-y	+= reset.c
+romstage-y	+= reset.c
+ramstage-y	+= reset.c
+
+endif
diff --git a/src/soc/amd/common/block/reset/reset.c b/src/soc/amd/common/block/reset/reset.c
new file mode 100644
index 0000000..b926553
--- /dev/null
+++ b/src/soc/amd/common/block/reset/reset.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <cf9_reset.h>
+#include <reset.h>
+#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/reset.h>
+
+void do_cold_reset(void)
+{
+	set_cf9_reset_to_cold();
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void do_warm_reset(void)
+{
+	/* If warm resets are not supported, executed a cold reset */
+	if (!CONFIG(SOC_SUPPORTS_WARM_RESET))
+		do_cold_reset();
+
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void do_board_reset(void)
+{
+	do_cold_reset();
+}