Change in coreboot[master]: nb/intel/sandybridge: Introduce `disable_refresh_machine` function
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47612 )
Change subject: nb/intel/sandybridge: Introduce `disable_refresh_machine` function ......................................................................
nb/intel/sandybridge: Introduce `disable_refresh_machine` function
The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 23 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47612/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0837f3a..7257674 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1960,21 +1960,33 @@ MCHBAR32(GDCRTRAININGMOD) = 0; }
-static void write_op(ramctr_timing *ctrl, int channel) +static void disable_refresh_machine(ramctr_timing *ctrl) { - int slotrank; + int channel;
- wait_for_iosav(channel); + FOR_ALL_POPULATED_CHANNELS { + /* choose an existing rank */ + const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31);
- iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); + /* Execute command queue */ + iosav_run_once(channel);
- /* Execute command queue */ - iosav_run_once(channel); + wait_for_iosav(channel);
- wait_for_iosav(channel); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); + } + + /* Refresh disable */ + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); + + FOR_ALL_POPULATED_CHANNELS { + /* Execute the same command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); + } }
/* @@ -1997,16 +2009,7 @@ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);
- FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - } + disable_refresh_machine(ctrl);
/* Enable write leveling on all ranks Disable all DQ outputs @@ -2175,38 +2178,7 @@
static void reprogram_320c(ramctr_timing *ctrl) { - int channel, slotrank; - - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* Choose an existing rank */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } + disable_refresh_machine(ctrl);
/* JEDEC reset */ dram_jedecreset(ctrl);
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47612 )
Change subject: nb/intel/sandybridge: Introduce `disable_refresh_machine` function ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47612 )
Change subject: nb/intel/sandybridge: Introduce `disable_refresh_machine` function ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47612/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47612/1/src/northbridge/intel/sandy... PS1, Line 1986: iosav_run_once(channel); This just works because the IOSAV sequence was programmed earlier, and it's just a dummy command anyway.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47612 )
Change subject: nb/intel/sandybridge: Introduce `disable_refresh_machine` function ......................................................................
Patch Set 5: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47612 )
Change subject: nb/intel/sandybridge: Introduce `disable_refresh_machine` function ......................................................................
nb/intel/sandybridge: Introduce `disable_refresh_machine` function
The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 23 insertions(+), 51 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 893d6b2..885689c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1933,21 +1933,33 @@ MCHBAR32(GDCRTRAININGMOD) = 0; }
-static void write_op(ramctr_timing *ctrl, int channel) +static void disable_refresh_machine(ramctr_timing *ctrl) { - int slotrank; + int channel;
- wait_for_iosav(channel); + FOR_ALL_POPULATED_CHANNELS { + /* choose an existing rank */ + const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31);
- iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); + /* Execute command queue */ + iosav_run_once(channel);
- /* Execute command queue */ - iosav_run_once(channel); + wait_for_iosav(channel);
- wait_for_iosav(channel); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); + } + + /* Refresh disable */ + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); + + FOR_ALL_POPULATED_CHANNELS { + /* Execute the same command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); + } }
/* @@ -1970,16 +1982,7 @@ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);
- FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - } + disable_refresh_machine(ctrl);
/* Enable write leveling on all ranks Disable all DQ outputs @@ -2142,38 +2145,7 @@
static void reprogram_320c(ramctr_timing *ctrl) { - int channel, slotrank; - - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* Choose an existing rank */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } + disable_refresh_machine(ctrl);
/* JEDEC reset */ dram_jedecreset(ctrl);
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Felix Held (Code Review)