Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/27262
Change subject: intel/common/block/systemagent: Add provision to configure PCIEXBAR from soc ......................................................................
intel/common/block/systemagent: Add provision to configure PCIEXBAR from soc
This implementation adds provision to configure SOC specific PCIEXBAR.
Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e958518a Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/skylake/Kconfig 6 files changed, 28 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/27262/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4577e76..a172e43 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -133,6 +133,12 @@ bool default y
+config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + help + This option allows you to select MMIO Base Address of PCI Express. + config PCR_BASE_ADDRESS hex default 0xd0000000 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 101d71e..1f9316e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -161,6 +161,12 @@ hex default 0x200000
+config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + help + This option allows you to select MMIO Base Address of PCI Express. + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573..d7619a0 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,10 +3,6 @@ help Intel Processor common System Agent support
-config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config SA_PCIEX_LENGTH hex default 0x10000000 if (PCIEX_LENGTH_256MB) diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 609e159..1c13e17 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,6 +24,10 @@ #include "systemagent_def.h" #include <timer.h>
+#if !defined(CONFIG_MMCONF_BASE_ADDRESS) || !CONFIG_MMCONF_BASE_ADDRESS +#error "PCI Express MMIO base address (PCIEXBAR) needs to be non-zero!" +#endif + #if !ENV_RAMSTAGE void bootblock_systemagent_early_init(void) { diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 6c366f1..236b06c 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -90,6 +90,12 @@ int default 16
+config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + help + This option allows you to select MMIO Base Address of PCI Express. + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3e0158b..b193e07 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -154,6 +154,12 @@ hex default 0x400000
+config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + help + This option allows you to select MMIO Base Address of PCI Express. + config PCR_BASE_ADDRESS hex default 0xfd000000