Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47568 )
Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ......................................................................
nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM
Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz.
Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47568/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 095d853..d166292 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -769,13 +769,14 @@ { u16 pasr, cwl, mr2reg; odtmap odt; - int srt; + int srt = 0;
pasr = 0; cwl = ctrl->CWL - 5; odt = get_ODT(ctrl, channel);
- srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; + if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) + srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh;
mr2reg = 0; mr2reg = (mr2reg & ~0x07) | pasr;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47568
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ......................................................................
nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM
Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47568/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47568 )
Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/47568/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47568/3//COMMIT_MSG@7 PS3, Line 7: SRT Just wondering: What is SRT?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47568 )
Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47568/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47568/3//COMMIT_MSG@7 PS3, Line 7: SRT
Just wondering: What is SRT?
CB:47567 has a commit message where "SRT" doesn't appear, but "Self-Refresh Temperature" does. I'm sure JESD79-3F will explain it better than I (because I am still not sure of what it is).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47568 )
Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47568/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47568/3//COMMIT_MSG@7 PS3, Line 7: SRT
CB:47567 has a commit message where "SRT" doesn't appear, but "Self-Refresh Temperature" does. […]
As to why disabling it can be desired... it may avoid problems with S3 resume and RAM that supports this feature (since the code used to be wrong).
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47568 )
Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ......................................................................
nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM
Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47568 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4d478a0..453222e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -759,13 +759,14 @@ { u16 pasr, cwl, mr2reg; odtmap odt; - int srt; + int srt = 0;
pasr = 0; cwl = ctrl->CWL - 5; odt = get_ODT(ctrl, channel);
- srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; + if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) + srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh;
mr2reg = 0; mr2reg = (mr2reg & ~0x07) | pasr;
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)