Change in coreboot[master]: soc/intel/alderlake: Add timestamp for cse_fw_sync

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60135 )

Change subject: soc/intel/alderlake: Add timestamp for cse_fw_sync
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60135/comment/e6d42183_30b0bfb3 
PS1, Line 14: (77,973)
> 77 ms is quite long. […]

This is expected on my board (which is based on ES silicon). I have measured cse_fw_sync() call during warm reboot time on QS Silicon, I see it only takes 2.3ms.

948:starting CSE firmware sync                        589,639 (338)
 949:finished CSE firmware sync                        591,982 (2,343)