Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44987 )
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry. This adds the public key signing token to the PSP Directory table to verify the signed PSP verstage binary
BUG=b:166100797 TEST=Build in a file and verify that it's present with the correct ID. BRANCH=Zork
Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44987/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 299ed0c..f385068 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -308,6 +308,7 @@ AMD_FW_PSP_WHITELIST = 0x3a, AMD_FW_L2_PTR = 0x40, AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, @@ -364,6 +365,7 @@ { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, + { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, { .type = AMD_FW_INVALID }, };
@@ -1085,8 +1087,8 @@ LONGOPT_SPI_MICRON_FLAG = 258, };
-// Unused values: DE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:"; +// Unused values: D +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:";
static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1119,6 +1121,7 @@ {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, {"verstage", required_argument, 0, 'Z' }, + {"verstage_sig", required_argument, 0, 'E' }, /* BIOS Directory Table items */ {"instance", required_argument, 0, 'I' }, {"apcb", required_argument, 0, 'a' }, @@ -1536,6 +1539,10 @@ register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); sub = instance = 0; break; + case 'E': + register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); + sub = instance = 0; + break; case 'C': soc_id = identify_platform(optarg); if (soc_id == PLATFORM_UNKNOWN) {
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44987 )
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44987/1/util/amdfwtool/amdfwtool.c File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/44987/1/util/amdfwtool/amdfwtool.c@... PS1, Line 1091: static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:"; line over 96 characters
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44987
to look at the new patch set (#2).
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry. This adds the public key signing token to the PSP Directory table to verify the signed PSP verstage binary
BUG=b:166100797 TEST=Build in a file and verify that it's present with the correct ID. BRANCH=Zork
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44987/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44987 )
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44987 )
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
Patch Set 2: Code-Review+2
Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44987 )
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
Patch Set 2: Code-Review+1
Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44987 )
Change subject: util/amdfwtool: Add PSP verstage signature entry ......................................................................
util/amdfwtool: Add PSP verstage signature entry
Add the field for the PSP verstage signature entry. This adds the public key signing token to the PSP Directory table to verify the signed PSP verstage binary
BUG=b:166100797 TEST=Build in a file and verify that it's present with the correct ID. BRANCH=Zork
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Eric Peers epeers@google.com --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved Eric Peers: Looks good to me, but someone else must approve
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 299ed0c..f385068 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -308,6 +308,7 @@ AMD_FW_PSP_WHITELIST = 0x3a, AMD_FW_L2_PTR = 0x40, AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, @@ -364,6 +365,7 @@ { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 }, { .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH }, + { .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH }, { .type = AMD_FW_INVALID }, };
@@ -1085,8 +1087,8 @@ LONGOPT_SPI_MICRON_FLAG = 258, };
-// Unused values: DE -static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:"; +// Unused values: D +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:z:J:B:K:L:Y:N:UW:I:a:Q:V:e:v:j:y:G:O:X:F:H:o:f:l:hZ:qR:P:C:E:";
static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -1119,6 +1121,7 @@ {"token-unlock", no_argument, 0, 'U' }, {"whitelist", required_argument, 0, 'W' }, {"verstage", required_argument, 0, 'Z' }, + {"verstage_sig", required_argument, 0, 'E' }, /* BIOS Directory Table items */ {"instance", required_argument, 0, 'I' }, {"apcb", required_argument, 0, 'a' }, @@ -1536,6 +1539,10 @@ register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg); sub = instance = 0; break; + case 'E': + register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg); + sub = instance = 0; + break; case 'C': soc_id = identify_platform(optarg); if (soc_id == PLATFORM_UNKNOWN) {
-
Aaron Durbin (Code Review) -
build bot (Jenkins) (Code Review)
-
Eric Peers (Code Review)
-
Furquan Shaikh (Code Review)
-
Martin Roth (Code Review)
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Raul Rangel (Code Review)