Change in coreboot[master]: soc/intel/elkhartlake: Expose FIVR config to mainboard

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Werner Zeh, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55861

to look at the new patch set (#4).

Change subject: soc/intel/elkhartlake: Expose FIVR config to mainboard
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soc/intel/elkhartlake: Expose FIVR config to mainboard

Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.

This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.

Signed-off-by: Lean Sheng Tan 
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
---
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
2 files changed, 75 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/55861/4