[M] Change in coreboot[main]: mb/google/brox: Fix memory config

[Shelley Chen (Code Review)]

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79355?usp=email )

Change subject: mb/google/brox: Fix memory config
......................................................................

Patch Set 7:

(1 comment)

File src/mainboard/google/brox/variants/baseboard/brox/memory.c:

https://review.coreboot.org/c/coreboot/+/79355/comment/beff2e1f_a813c699 :
PS7, Line 13: .lpx_dq_map = {
            : 		.ddr0 = {
            : 			.dq0 = { 4,  7, 5,  6,  0,  1,  2,  3, },
            : 			.dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, },
            : 		},
            : 		.ddr1 = {
            : 			.dq0 = {  1,  2,  3,  0, 6,  4, 7,  5, },
            : 			.dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, },
            : 		},
            : 		.ddr2 = {
            : 			.dq0 = {  0,  3,  2,  1, 6,  5, 7,  4, },
            : 			.dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, },
            : 		},
            : 		.ddr3 = {
            : 			.dq0 = {  5, 7,  4, 6,  2,  0,  1,  3, },
            : 			.dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, },
            : 		},
            : 		.ddr4 = {
            : 			.dq0 = { 4,  6, 5,  7,  3,  2,  1,  0, },
            : 			.dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, },
            : 		},
            : 		.ddr5 = {
            : 			.dq0 = {  2,  1,  3,  0, 6,  4, 7,  5, },
            : 			.dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, },
            : 		},
            : 		.ddr6 = {
            : 			.dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, },
            : 			.dq1 = {  1,  2,  3,  0, 5,  6,  7, 4, },
            : 		},
            : 		.ddr7 = {
            : 			.dq0 = { 3, 6,  2,  7,  5,  0,  1,  4, },
            : 			.dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, },
            : 		},
            : 	},
            : 
            : 	/* DQS CPU<>DRAM map */
            : 	.lpx_dqs_map = {
            : 		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
            : 		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
            : 	},
            : 
            : 	.lp5x_config = {
            : 		.ccc_config = 0x99,
            : 	},
> Where did you get these values from?

Hi Paul, as mentioned in the comments this was from the brox schematics and defines how the Soc connects to the DRAM.  Unfortunately, the schematics are not open right now, but the way that these connections are defined are done exactly the same way as other existing Intel boards.