Change in coreboot[master]: soc/intel/alderlake/acpi: Skip D3Cold for TBT

[Furquan Shaikh (Code Review)]

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Alex Levin, Sugnan Prabhu S, Rizwan Qureshi, Subramony Sesha (Anand), Ruben Rodriguez Buchillon, Aamir Bohra, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51274 )

Change subject: soc/intel/alderlake/acpi: Skip D3Cold for TBT
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Patch Set 3:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/51274/comment/82f116ef_7b07af2f 
PS3, Line 9: Includes change to skip D3Cold when TBT is in disconnected state which
           : was blocking the S0ix state transition.
> Let's please address the opens and understand the reason for this change before pushing this in.

Marking as resolved for now to move this change forward for validation. But, I would still like to get the opens answered.

File src/soc/intel/alderlake/acpi/tcss.asl:

https://review.coreboot.org/c/coreboot/+/51274/comment/3ed870bd_21349f68 
PS3, Line 616: _SB.PCI0.TDM1.IFWR()
> The IFWR Method doesn't seem to be necessary, you could just check `_SB.PCI0.TDM1. […]

Sugnan - can you please address Tim's comment? We can go ahead and land this to unblock the validation. But, let's continue addressing the opens in b/183670327 even after this change lands.