Change in coreboot[master]: mainboard/ocp/wedge100s: Add vboot support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29593

Change subject: mainboard/ocp/wedge100s: Add vboot support
......................................................................

mainboard/ocp/wedge100s: Add vboot support

* Add RO only FMAP.
* Add kconfig options.

Tested=OCP Wedge100s

Change-Id: I1979e0263e41f21c01c407ac81ad1198a53741e8
Signed-off-by: Philipp Deppenwiese 
---
M src/mainboard/ocp/wedge100s/Kconfig
A src/mainboard/ocp/wedge100s/vboot-ro.fmd
2 files changed, 30 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29593/1

diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index 5d4349d..9c10d7d 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -16,6 +16,14 @@
    select MAINBOARD_HAS_LPC_TPM
    select MAINBOARD_HAS_TPM1

+config VBOOT
+	select VBOOT_VBNV_CMOS
+	select VBOOT_NO_BOARD_SUPPORT
+	select GBB_FLAG_DISABLE_LID_SHUTDOWN
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_FWMP
+
 config MAINBOARD_DIR
    string
    default "ocp/wedge100s"
@@ -31,6 +39,7 @@
 config CBFS_SIZE
    hex
    default 0x00200000
+	default 0x006fa000 if VBOOT

config VIRTUAL_ROM_SIZE
    hex
@@ -46,5 +55,6 @@
 config FMDFILE
    string
    default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if VBOOT

endif # BOARD_OCP_WEDGE100S
diff --git a/src/mainboard/ocp/wedge100s/vboot-ro.fmd b/src/mainboard/ocp/wedge100s/vboot-ro.fmd
new file mode 100644
index 0000000..81b4cb8
--- /dev/null
+++ b/src/mainboard/ocp/wedge100s/vboot-ro.fmd
@@ -0,0 +1,20 @@
+FLASH 16M {
+	SI_ALL@0x0 0x800000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x7ff000
+	}
+	SI_BIOS@0x800000 0x800000 {
+		RW_MRC_CACHE@0x0 0x10000
+		RW_VPD@0x010000 0x2000
+		WP_RO@0x012000 0x7ee000 {
+			RO_VPD@0x0 0x4000
+			RO_SECTION@0x4000 0x7ea000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x6fa000
+			}
+		}
+	}
+}