Change in coreboot[master]: nb/intel/ironlake: Put host bridge registers into its own file
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43726 )
Change subject: nb/intel/ironlake: Put host bridge registers into its own file ......................................................................
nb/intel/ironlake: Put host bridge registers into its own file
Looks like some registers are defined twice. Also, group some QPI registers together. They were scattered around and mixed with the host bridge registers, probably because other northbridges have such registers in the host bridge's PCI config space. But not Ironlake.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/ironlake.h 2 files changed, 50 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43726/1
diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h new file mode 100644 index 0000000..c5341cb --- /dev/null +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__ +#define __IRONLAKE_HOSTBRIDGE_REGS_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 + +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ + +#define D0F0_CAPID0 0xe0 + +#define TSEG 0xac /* TSEG base */ + +/* FIXME: Deduplicate these registers */ +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define LAC 0x87 /* Legacy Access Control */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +#endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 92ee76c..5a1d52e 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -12,37 +12,6 @@ #define IOMMU_BASE4 0xfed93000
/* - * D0:F0 - */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ - -#define D0F0_CAPID0 0xe0 - -#define TSEG 0xac /* TSEG base */ - -/* * D1:F0 PEG */ #define PEG_CAP 0xa2 @@ -76,17 +45,14 @@
/* Device 0:0.0 PCI configuration space (Host Bridge) */
-#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define X60BAR 0x60 +#include "hostbridge_regs.h"
-#define LAC 0x87 /* Legacy Access Control */ +/* + * QPI D0:F1 + */ +#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
-#define SKPAD 0xdc /* Scratchpad Data */ -
/* Device 0:2.0 PCI configuration space (Graphics Device) */
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43726 )
Change subject: nb/intel/ironlake: Put host bridge registers into its own file ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43726 )
Change subject: nb/intel/ironlake: Put host bridge registers into its own file ......................................................................
nb/intel/ironlake: Put host bridge registers into its own file
Looks like some registers are defined twice. Also, group some QPI registers together. They were scattered around and mixed with the host bridge registers, probably because other northbridges have such registers in the host bridge's PCI config space. But not Ironlake.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- A src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/ironlake.h 2 files changed, 50 insertions(+), 39 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h new file mode 100644 index 0000000..c5341cb --- /dev/null +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__ +#define __IRONLAKE_HOSTBRIDGE_REGS_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 + +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ + +#define D0F0_CAPID0 0xe0 + +#define TSEG 0xac /* TSEG base */ + +/* FIXME: Deduplicate these registers */ +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define LAC 0x87 /* Legacy Access Control */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +#endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 92ee76c..5a1d52e 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -12,37 +12,6 @@ #define IOMMU_BASE4 0xfed93000
/* - * D0:F0 - */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ - -#define D0F0_CAPID0 0xe0 - -#define TSEG 0xac /* TSEG base */ - -/* * D1:F0 PEG */ #define PEG_CAP 0xa2 @@ -76,17 +45,14 @@
/* Device 0:0.0 PCI configuration space (Host Bridge) */
-#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define X60BAR 0x60 +#include "hostbridge_regs.h"
-#define LAC 0x87 /* Legacy Access Control */ +/* + * QPI D0:F1 + */ +#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */
-#define SKPAD 0xdc /* Scratchpad Data */ -
/* Device 0:2.0 PCI configuration space (Graphics Device) */
-
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