[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Harsha B R, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69741 )

Change subject: mb/intel/mtlrvp: Add romstage and configure LP5 memory parts
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Patch Set 10:

(1 comment)

File src/mainboard/intel/mtlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/69741/comment/73028eed_7de79512 
PS10, Line 23: 	spd_index = 1;
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/adlrvp/...