Change in coreboot[master]: sb/intel/common: Use common save_state ops to fetch apmc args
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37011 )
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 89 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/1
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f292b6f..a9942f3 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> @@ -38,6 +37,11 @@ return gnvs; }
+void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +} + int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -162,18 +166,6 @@ xhci_sleep(slp_type); }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((u32)state->rbx); - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 6af8805..8959613 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -18,7 +18,6 @@ #define INTEL_COMMON_PMUTIL_H
#include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h>
#define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -142,10 +141,10 @@ void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); +void set_gnvs(void *gnvs_ptr); uint8_t get_gnvs_smif(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); +int smi_apmc_find_state_save_node(u8 cmd); void pch_log_state(void);
#endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 46fe28a..80f4380 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <inttypes.h> #include <types.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -22,7 +23,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> @@ -214,76 +214,108 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +int smi_apmc_find_state_save_node(u8 cmd) { - em64t101_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node;
/* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0 == 1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4 == 0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) {
- return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; }
- return NULL; + return -1; }
static void southbridge_smi_gsmi(void) { - u32 *ret, *param; + u32 ret, param; u8 sub_command; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops();
- if (!io_smi) + if (node < -1) return;
/* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; - sub_command = (u8)(*ret >> 8); + uint64_t reg; + if (ops->get_reg(node, RAX, ®)) + return; + sub_command = (u8)(reg >> 8);
/* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + if (ops->get_reg(node, RBX, ®)) + return; + param = reg & UINT32_MAX;
/* drivers/elog/gsmi.c */ - *ret = gsmi_exec(sub_command, param); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); }
static void southbridge_smi_store(void) { u8 sub_command, ret; - em64t101_smm_state_save_area_t *io_smi = - smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uintptr_t reg_rbx; + void *param; + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops();
- if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, ®)) + return; + sub_command = (u8)(reg >> 8);
/* Parameter buffer in EBX */ - reg_rbx = (uintptr_t)io_smi->rbx; + if (ops->get_reg(node, RBX, ®)) + return; + param = (void *)(uint32_t)reg;
/* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_rbx); - io_smi->rax = ret; + ret = smmstore_exec(sub_command, param); + ops->set_reg(node, RAX, ret); +} + +static void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +{ + int node = smi_apmc_find_state_save_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); + uint64_t rbx; + uintptr_t gnvs_ptr; + if (ops->get_reg(node, RBX, &rbx)) + return; + + gnvs_ptr = rbx; + + set_gnvs((void *)gnvs_ptr); + *smm_done = 1; + + printk(BIOS_DEBUG, "SMI#: Setting GNVS to " PRIxPTR"\n", gnvs_ptr); }
static int mainboard_finalized = 0; diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 1aacbca..b215cc6 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -36,17 +36,15 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; +static global_nvs_t *gnvs;
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) +void set_gnvs(void *gnvs_ptr) { - gnvs = *(global_nvs_t **)0x500; - *smm_done = 1; + gnvs = gnvs_ptr; }
int southbridge_io_trap_handler(int smif) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 96a9e2a..2c56fe6 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -28,9 +28,12 @@ /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs; + +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +}
int southbridge_io_trap_handler(int smif) { @@ -49,14 +52,6 @@ return 0; }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - uint8_t get_gnvs_smif(void) { return gnvs->smif; diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6ed5edd..eb193fa 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -26,18 +26,12 @@
#include "nvs.h"
-/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ -u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; +static global_nvs_t *gnvs;
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +void set_gnvs(void *gnvs_ptr) +{ + gnvs = gnvs_ptr; +}
int southbridge_io_trap_handler(int smif) { @@ -56,14 +50,6 @@ return 0; }
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - uint8_t get_gnvs_smif(void) { return gnvs->smif; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3668842..ac45c15 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t101_save_state.h> #include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h>
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37011
to look at the new patch set (#2).
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 94 insertions(+), 100 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37011
to look at the new patch set (#3).
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 94 insertions(+), 100 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37011
to look at the new patch set (#5).
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 94 insertions(+), 100 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/5
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37011
to look at the new patch set (#6).
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 95 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/6
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37011
to look at the new patch set (#7).
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 95 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/7
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37011
to look at the new patch set (#8).
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
sb/intel/common: Use common save_state ops to fetch apmc args
Change-Id: If48671f5a92a533fe7ab01ac1fb7bfcb00dafdd5 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 95 insertions(+), 101 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/37011/8
Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37011 )
Change subject: sb/intel/common: Use common save_state ops to fetch apmc args ......................................................................
Abandoned
superseded in common_smm_save_state
-
Arthur Heymans (Code Review)