[L] Change in coreboot[main]: Introduce a coreboot Control Block (CCB)

[Arthur Heymans (Code Review)]

Attention is currently required from: Angel Pons, Felix Held, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Paul Menzel, Simon Glass, Simon Glass.

Arthur Heymans has posted comments on this change by Simon Glass. ( https://review.coreboot.org/c/coreboot/+/77712?usp=email )

Change subject: Introduce a coreboot Control Block (CCB)
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Patch Set 10:

(1 comment)

Patchset:

PS10:
> My objection is the -2. I am happy to address comments but there is no point if the whole thing is blocked.
>
> The tricky thing here is reading the CCB early enough that it can affect the first console output. Putting the CCB in the bootblock is simpler on some boards since it doesn't require reading the SPI flash very early in bootblock (before console).

So reading SPI flash is basically free on x86. On others ofc it isn't, changing the bootblock post boot on other ARCH is often tricky as there is some header with checksum that needs updating.

So I can't speak for Julius but it looks like the problem is that there are already quite a few mechanism for configuration post build and that adding a new one fragments the ecosystem. Your problem with those existing ones is that they happen too late in the boot process and that some messages get printed before that code is reached. Do I assume correct that the slowness of uart for those first few messages is the main problem?

It looks like it's more a problem with defaults and how the codeflow works and not so much with configuration mechanisms.

So the rationale behind setting up console first, before other mechanisms can be used/reached for setting options is that you want a console to debug those mechanism. Maybe the solution is not a simpler mechanism like CBB but a buildtime (Kconfig) option to move console init a bit later? Setting up a SPI controller to use for instance VPD is not that much more complicated than setting up uart.

Alternatively and maybe better: Only print to memory initially. Other (slow) consoles are disabled at the start. Once existing mechanisms for post build configuration can be reached and the config options is to enable those slow uarts, print out what is inside the memory buffer to uart.