Change in coreboot[master]: mb/google/zork/mainboard: Remove unused pirq_data

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48666 )

Change subject: mb/google/zork/mainboard: Remove unused pirq_data
......................................................................

mb/google/zork/mainboard: Remove unused pirq_data

This table was wrong. It's also produced by the SoC now.

BUG=b:170595019
TEST=Verify PCI IRQ: log messages

Signed-off-by: Raul E Rangel 
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
---
M src/mainboard/google/zork/mainboard.c
1 file changed, 0 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48666/1

diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index 824a87d..94a64bd 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -51,30 +51,6 @@
    "PIC and APIC FCH interrupt tables must be the same size");

/*
- * This table doesn't actually perform any routing. It only populates the
- * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified
- * in fch_apic_routing. The linux kernel only looks at this field as a backup
- * if ACPI routing fails to describe the PCI routing correctly. The linux kernel
- * also uses the APIC by default, so the value coded into the registers will be
- * wrong.
- *
- * This table is also confusing because PCI Interrupt routing happens at the
- * device/slot level, not the function level.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	{ PCIE_GPP_0_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_1_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi
-	{ PCIE_GPP_2_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD
-	{ PCIE_GPP_3_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_4_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_5_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_6_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME
-	{ PCIE_GPP_A_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_B_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ SMBUS_DEVFN,	{ PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
-};
-
-/*
  * This controls the device -> IRQ routing.
  *
  * Hardcoded IRQs:
@@ -133,9 +109,6 @@
 static void pirq_setup(void)
 {
    init_tables();
-
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
    intr_data_ptr = fch_apic_routing;
    picr_data_ptr = fch_pic_routing;
 }

[Nikolai Vyssotski (Code Review)]

Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48666 )

Change subject: mb/google/zork/mainboard: Remove unused pirq_data
......................................................................

Patch Set 1: Code-Review+1

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48666 )

Change subject: mb/google/zork/mainboard: Remove unused pirq_data
......................................................................

Patch Set 1: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48666 )

Change subject: mb/google/zork/mainboard: Remove unused pirq_data
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48666/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48666/1//COMMIT_MSG@9 
PS1, Line 9: SoC
nit: SoC code

[Raul Rangel (Code Review)]

Hello build bot (Jenkins), Marshall Dawson, Nikolai Vyssotski, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48666

to look at the new patch set (#2).

Change subject: mb/google/zork/mainboard: Remove unused pirq_data
......................................................................

mb/google/zork/mainboard: Remove unused pirq_data

This table was wrong. It's also produced by the SoC code now.

BUG=b:170595019
TEST=Verify PCI IRQ: log messages

Signed-off-by: Raul E Rangel 
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
---
M src/mainboard/google/zork/mainboard.c
1 file changed, 0 insertions(+), 27 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48666/2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48666 )

Change subject: mb/google/zork/mainboard: Remove unused pirq_data
......................................................................

mb/google/zork/mainboard: Remove unused pirq_data

This table was wrong. It's also produced by the SoC code now.

BUG=b:170595019
TEST=Verify PCI IRQ: log messages

Signed-off-by: Raul E Rangel 
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666
Tested-by: build bot (Jenkins) 
Reviewed-by: Nikolai Vyssotski 
Reviewed-by: Felix Held 
---
M src/mainboard/google/zork/mainboard.c
1 file changed, 0 insertions(+), 27 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Nikolai Vyssotski: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index 824a87d..94a64bd 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -51,30 +51,6 @@
    "PIC and APIC FCH interrupt tables must be the same size");

/*
- * This table doesn't actually perform any routing. It only populates the
- * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified
- * in fch_apic_routing. The linux kernel only looks at this field as a backup
- * if ACPI routing fails to describe the PCI routing correctly. The linux kernel
- * also uses the APIC by default, so the value coded into the registers will be
- * wrong.
- *
- * This table is also confusing because PCI Interrupt routing happens at the
- * device/slot level, not the function level.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	{ PCIE_GPP_0_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_1_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi
-	{ PCIE_GPP_2_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD
-	{ PCIE_GPP_3_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_4_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_5_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_6_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME
-	{ PCIE_GPP_A_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ PCIE_GPP_B_DEVFN,	{ PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
-	{ SMBUS_DEVFN,	{ PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
-};
-
-/*
  * This controls the device -> IRQ routing.
  *
  * Hardcoded IRQs:
@@ -133,9 +109,6 @@
 static void pirq_setup(void)
 {
    init_tables();
-
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
    intr_data_ptr = fch_apic_routing;
    picr_data_ptr = fch_pic_routing;
 }