New patch to review for coreboot: soc/intel/apollolake: Fix northbridge _CRS

[Lijian Zhao]

Lijian Zhao ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14288

-gerrit

commit 07110b1932fbfe0d5e6206465c829360c71b4cc6
Author: Zhao, Lijian 
Date:   Thu Apr 7 15:50:03 2016 -0700

soc/intel/apollolake: Fix northbridge _CRS

Build break on current _CRS defination: within CRS, point to
    correct parent as MCHC but not MCHC._CRS

Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e
    Signed-off-by: Zhao, Lijian 
---
 src/soc/intel/apollolake/acpi/northbridge.asl | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 1349c6a..9f4be7c 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -88,9 +88,9 @@ Method (_CRS, 0, Serialized)
    CreateDwordField (MCRS, ^PM01._LEN, PLEN)

/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
-	And(^MCHC.TLUD, 0xFFF00000, PMIN)
+	And(^^MCHC.TLUD, 0xFFF00000, PMIN)
    /* Read MMCONF base */
-	And(^MCHC.MCNF, 0xF0000000, PMAX)
+	And(^^MCHC.MCNF, 0xF0000000, PMAX)

/* Calculate PCI MMIO Length */
    Add(Subtract(PMAX, PMIN), 1, PLEN)
@@ -101,10 +101,10 @@ Method (_CRS, 0, Serialized)
    CreateDwordField(MCRS, ^STOM._LEN, GLEN)

/* Read BGSM */
-	And(^MCHC.BGSM, 0xFFF00000, GMIN)
+	And(^^MCHC.BGSM, 0xFFF00000, GMIN)

/* Read TOLUD */
-	And(^MCHC.TLUD, 0xFFF00000, GMAX)
+	And(^^MCHC.TLUD, 0xFFF00000, GMAX)
    Decrement(GMAX)
    Add(Subtract(GMAX, GMIN), 1, GLEN)

@@ -113,7 +113,7 @@ Method (_CRS, 0, Serialized)
    CreateQwordField (MCRS, ^PM02._MAX, MMAX)
    CreateQwordField (MCRS, ^PM02._LEN, MLEN)

-	Store (^MCHC.TUUD, Local0)
+	Store (^^MCHC.TUUD, Local0)

If (LLessEqual (Local0, 0x1000000000)) {
    	Store (0, MMIN)
@@ -123,4 +123,4 @@ Method (_CRS, 0, Serialized)

Return (MCRS)
 }
-}
\ No newline at end of file
+}