Change in coreboot[master]: sb/intel/ibexpeak: Drop P_LVLx support in FADT

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55217 )

Change subject: sb/intel/ibexpeak: Drop P_LVLx support in FADT
......................................................................

sb/intel/ibexpeak: Drop P_LVLx support in FADT

IO MWAIT redirection is not enabled. The code is missing, but C-states
should instead be reported using the _CST ACPI object.

Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/mainboard/lenovo/t410/devicetree.cb
M src/mainboard/lenovo/x201/devicetree.cb
M src/southbridge/intel/ibexpeak/fadt.c
3 files changed, 3 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb
index a4f3463..e3456f2 100644
--- a/src/mainboard/lenovo/t410/devicetree.cb
+++ b/src/mainboard/lenovo/t410/devicetree.cb
@@ -49,7 +49,6 @@
    		register "gen3_dec" = "0x1c1681" # EC ?
    		register "gen4_dec" = "0x040069" # ?

-			register "c2_latency" = "1"
    		register "docking_supported" = "1"

register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index e142a1c..effe4ef 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -49,7 +49,6 @@
    		register "gen3_dec" = "0x1c1681"
    		register "gen4_dec" = "0x040069"

-			register "c2_latency" = "1"
    		register "docking_supported" = "1"

register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index ccd9f57..40c8bdc 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -11,7 +11,6 @@
    struct device *dev = pcidev_on_root(0x1f, 0);
    struct southbridge_intel_ibexpeak_config *chip = dev->chip_info;
    u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
-	int c2_latency;

fadt->sci_int = 0x9;

@@ -32,12 +31,9 @@
    fadt->pm2_cnt_len = 1;
    fadt->pm_tmr_len = 4;
    fadt->gpe0_blk_len = 16;
-	c2_latency = chip->c2_latency;
-	if (!c2_latency) {
-		c2_latency = 101; /* c2 unsupported */
-	}
-	fadt->p_lvl2_lat = c2_latency;
-	fadt->p_lvl3_lat = 87;
+	/* P_LVLx not used */
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
    /* P_CNT not supported */
    fadt->duty_offset = 0;
    fadt->duty_width = 0;
@@ -54,9 +50,6 @@
    if (chip->docking_supported) {
    	fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
    }
-	if (c2_latency < 100) {
-		fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
-	}

fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
    fadt->x_pm1a_evt_blk.bit_width = 32;