Change in coreboot[master]: soc/intel/tgl: add missing device UART #3 to chipset devicetree - coreboot-gerrit

6 Mar 2022


      Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62624 )
Change subject: soc/intel/tgl: add missing device UART #3 to chipset devicetree
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Patch Set 1:
This change is ready for review.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3abccf65d59278b38835cdfda9e54991d6edaacf
Gerrit-Change-Number: 62624
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner foss@mniewoehner.de
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Felix Singer felixsinger@posteo.net
Gerrit-Reviewer: Nico Huber nico.h@gmx.de
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@mailbox.org
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
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