Change in coreboot[master]: nb/intel/haswell: Align more stuff with Broadwell

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46981 )

Change subject: nb/intel/haswell: Align more stuff with Broadwell
......................................................................

nb/intel/haswell: Align more stuff with Broadwell

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I1ab3df0657e8e2fa074197b445bdce624b0d4d48
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/haswell/northbridge.c
3 files changed, 20 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46981/1

diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index cc4487c..0e7967f 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -33,8 +33,13 @@
    const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;

/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
-	if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) {
+	const bool emit_igd =
+			igfx_dev && igfx_dev->enabled &&
+			gfxvtbar && gfxvten &&
+			!MCHBAR32(GFXVTBAR + 4);

+	/* First, add DRHD entries */
+	if (emit_igd) {
    	const unsigned long tmp = current;

current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 28a33d8..0758cdf 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -175,10 +175,10 @@
    Name (_UID, 1)

Name (PDRS, ResourceTemplate () {
-		Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000)
-		Memory32Fixed (ReadWrite, DEFAULT_MCHBAR,   0x00008000)
-		Memory32Fixed (ReadWrite, DEFAULT_DMIBAR,   0x00001000)
-		Memory32Fixed (ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x4000)
+		Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x8000)
+		Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x1000)
+		Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x1000)
    	Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
    	Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
    	Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index a6f187c..64a274d 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -264,9 +264,8 @@
 static void mc_read_map_entries(struct device *dev, uint64_t *values)
 {
    int i;
-	for (i = 0; i < NUM_MAP_ENTRIES; i++) {
+	for (i = 0; i < NUM_MAP_ENTRIES; i++)
    	read_map_entry(dev, &memory_map[i], &values[i]);
-	}
 }

static void mc_report_map_entries(struct device *dev, uint64_t *values)
@@ -569,7 +568,7 @@
    northbridge_dmi_init();
    northbridge_topology_init();

-	/* Enable Power Aware Interrupt Routing. */
+	/* Enable Power Aware Interrupt Routing */
    pair = MCHBAR8(INTRDIRCTL);
    pair &= ~0x7;	/* Clear 2:0 */
    pair |= 0x4;	/* Fixed Priority */
@@ -586,7 +585,7 @@
    MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
    printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");

-	/* Configure turbo power limits 1ms after reset complete bit. */
+	/* Configure turbo power limits 1ms after reset complete bit */
    mdelay(1);
    set_power_limits(28);

@@ -595,12 +594,12 @@
 }

static struct device_operations mc_ops = {
-	.read_resources         = mc_read_resources,
-	.set_resources          = pci_dev_set_resources,
-	.enable_resources       = pci_dev_enable_resources,
-	.init                   = northbridge_init,
-	.acpi_fill_ssdt		= generate_cpu_entries,
-	.ops_pci                = &pci_dev_ops_pci,
+	.read_resources   = mc_read_resources,
+	.acpi_fill_ssdt   = generate_cpu_entries,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = northbridge_init,
+	.ops_pci          = &pci_dev_ops_pci,
 };

static const unsigned short mc_pci_device_ids[] = {
@@ -628,7 +627,7 @@

static void enable_dev(struct device *dev)
 {
-	/* Set the operations if it is a special bus type. */
+	/* Set the operations if it is a special bus type */
    if (dev->path.type == DEVICE_PATH_DOMAIN) {
    	dev->ops = &pci_domain_ops;
    } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {