Change in coreboot[master]: soc/intel/braswell: Add support for FSP MR2

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29661

Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................

soc/intel/braswell: Add support for FSP MR2

Actual FspUpdVpd.h does not match the MR2 version in fsp 3rdparty
Add config USE_BSWSBFSP to support FSP MR2

BUG=NA
TEST=Portwell PQ7-M107

Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/Kconfig
M src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
2 files changed, 39 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29661/1

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 50c2802..8b44d1d 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -128,4 +128,11 @@
    string
    default "soc/intel/braswell/bootblock/timestamp.inc"

+config USE_BSWSBFSP
+	bool "Use MR2 FSP"
+	default y
+	help
+	  FSP releases have difference image IDs. Enable this option when
+	  FSP MR2 is used.
+
 endif
diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
index 1ae1d03..265873d 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
@@ -1,6 +1,7 @@
 /** @file

Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2018, Eltan B.V.

Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
@@ -197,6 +198,7 @@
     Enable/Disable DDR3 Auto Self Refresh
 **/
   UINT8                       PcdDdr3AutoSelfRefreshEnable;
+/* NOT SUPPORTED BY MR2 START */
 /** Offset 0x0044
     Disable Auto Detect Dram for LPDDR3 memory
     To Enable/Disable AutoDetectDram
@@ -229,6 +231,7 @@
   UINT8                       PcdRxOdtLimitChannel1;
 /** Offset 0x004A
 **/
+/* NOT SUPPORTED BY MR2 END */
   UINT8                       ReservedMemoryInitUpd[182];
 } MEMORY_INIT_UPD;

@@ -485,6 +488,7 @@
     Check for Sd card detect
 **/
   UINT8                       PcdSdDetectChk;
+/* NOT SUPPORTED BY MR2 START */
 /** Offset 0x0163
 **/
   UINT8                       I2C0Frequency;
@@ -524,7 +528,8 @@
 /** Offset 0x016F
 **/
   UINT8                       D0VnnBump100mV;
-/** Offset 0x170
+ /* NOT SUPPORTED BY MR2 END */
+ ** Offset 0x170
 **/
   UINT8                       ReservedSiliconInitUpd[398];
 } SILICON_INIT_UPD;
@@ -558,13 +563,28 @@
 /** Offset 0x0100
 **/
   SILICON_INIT_UPD            SiliconInitUpd;
-/** Offset 0x0305
+/** Offset 0x02FE
 **/
   UINT16                      PcdRegionTerminator;
+
+#if IS_ENABLED(CONFIG_USE_BSWSBFSP)
+/** Offset 0x0300
+**/
+  UINT8                       UnusedUpdSpace4[2123];
+/** Offset 0x0B4B
+**/
+  UINT8                       PcdPaddingSpace;
+#endif //CONFIG_USE_BSWSBFSP
+
 } UPD_DATA_REGION;

+#if IS_ENABLED(CONFIG_USE_BSWSBFSP)
+#define FSP_IMAGE_ID    0x5053464253575342        /* 'BSWSBFSP' */
+#define FSP_IMAGE_REV   0x01010401 
+#else
 #define FSP_IMAGE_ID    0x2450534657534224        /* '$BSWFSP$' */
 #define FSP_IMAGE_REV   0x01010700
+#endif

typedef struct _VPD_DATA_REGION {
 /** Offset 0x0000
@@ -577,6 +597,16 @@
 /** Offset 0x000C
 **/
   UINT32                      PcdUpdRegionOffset;
+#if IS_ENABLED(CONFIG_USE_BSWSBFSP)
+/** Offset 0x0010
+**/
+  UINT8                       UnusedVpdSpace0[20];
+/** Offset 0x0024
+    Enable Secure Boot
+    Enable/disable secure boot. Auto by default.
+**/
+  UINT8                       PcdEnableSecureBoot;
+#endif
 } VPD_DATA_REGION;

#pragma pack(pop)