Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34909 )
Change subject: arch/x86: Rename some mainboard_romstage_entry() ......................................................................
arch/x86: Rename some mainboard_romstage_entry()
These platforms use different signature for this function, so declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/rambi/romstage.c M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 8 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34909/1
diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 8bc766e..ebe59ac 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -28,7 +28,7 @@ /* By default, don't do anything */ }
-void mainboard_romstage_entry(int s3_resume) +void mainboard_romstage_entry_s3(int s3_resume) { size_t num_gpios; const struct soc_amd_gpio *gpios; diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 5322267..9fbe1ca 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,7 +55,7 @@ return &spd_file_content[SPD_SIZE * ram_id]; }
-void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_romstage_entry_rp(struct romstage_params *rp) { void *spd_content; int dual_channel = 0; diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index d8b2900..c0d03d0e 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __PICASSO_ROMSTAGE_H__ #define __PICASSO_ROMSTAGE_H__
-void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume);
#endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 22b5ce4..7970b0e 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -34,7 +34,7 @@
#include "chip.h"
-void __weak mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } @@ -49,7 +49,7 @@
console_init();
- mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume);
if (!s3_resume) { post_code(0x40); diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6ce79b4..598b409 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __STONEYRIDGE_ROMSTAGE_H__ #define __STONEYRIDGE_ROMSTAGE_H__
-void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume);
#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 4cadc68..2dce5b1 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -97,7 +97,7 @@ if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1();
- mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume);
bsp_agesa_call();
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3dc24f0..305cf27 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -28,7 +28,7 @@ struct mrc_params *mrc_params; };
-void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_romstage_entry_rp(struct romstage_params *params); void romstage_common(struct romstage_params *params);
void raminit(struct mrc_params *mp, int prev_sleep_state); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cf6a856..b130c39 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -144,7 +144,7 @@ gfx_init();
/* Call into mainboard. */ - mainboard_romstage_entry(&rp); + mainboard_romstage_entry_rp(&rp);
if (CONFIG(SMM_TSEG)) smm_list_regions();
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34909
to look at the new patch set (#2).
Change subject: arch/x86: Rename some mainboard_romstage_entry() ......................................................................
arch/x86: Rename some mainboard_romstage_entry()
These platforms use different signature for this function, so declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/rambi/romstage.c M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 8 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34909/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34909 )
Change subject: arch/x86: Rename some mainboard_romstage_entry() ......................................................................
Patch Set 4: Code-Review+1
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34909 )
Change subject: arch/x86: Rename some mainboard_romstage_entry() ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34909 )
Change subject: arch/x86: Rename some mainboard_romstage_entry() ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34909 )
Change subject: arch/x86: Rename some mainboard_romstage_entry() ......................................................................
arch/x86: Rename some mainboard_romstage_entry()
These platforms use different signature for this function, so declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/rambi/romstage.c M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 8 files changed, 10 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 8bc766e..ebe59ac 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -28,7 +28,7 @@ /* By default, don't do anything */ }
-void mainboard_romstage_entry(int s3_resume) +void mainboard_romstage_entry_s3(int s3_resume) { size_t num_gpios; const struct soc_amd_gpio *gpios; diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 5322267..9fbe1ca 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,7 +55,7 @@ return &spd_file_content[SPD_SIZE * ram_id]; }
-void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_romstage_entry_rp(struct romstage_params *rp) { void *spd_content; int dual_channel = 0; diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index d8b2900..c0d03d0e 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __PICASSO_ROMSTAGE_H__ #define __PICASSO_ROMSTAGE_H__
-void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume);
#endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 22b5ce4..7970b0e 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -34,7 +34,7 @@
#include "chip.h"
-void __weak mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } @@ -49,7 +49,7 @@
console_init();
- mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume);
if (!s3_resume) { post_code(0x40); diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6ce79b4..598b409 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -16,6 +16,6 @@ #ifndef __STONEYRIDGE_ROMSTAGE_H__ #define __STONEYRIDGE_ROMSTAGE_H__
-void mainboard_romstage_entry(int s3_resume); +void mainboard_romstage_entry_s3(int s3_resume);
#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 4cadc68..c76f7cd 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -37,7 +37,7 @@
#include "chip.h"
-void __weak mainboard_romstage_entry(int s3_resume) +void __weak mainboard_romstage_entry_s3(int s3_resume) { /* By default, don't do anything */ } @@ -97,7 +97,7 @@ if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) load_smu_fw1();
- mainboard_romstage_entry(s3_resume); + mainboard_romstage_entry_s3(s3_resume);
bsp_agesa_call();
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 8ea2d69..ae38b70 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -28,7 +28,7 @@ struct mrc_params *mrc_params; };
-void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_romstage_entry_rp(struct romstage_params *params); void romstage_common(struct romstage_params *params);
void raminit(struct mrc_params *mp, int prev_sleep_state); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7a413d9..63e36aa 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -146,7 +146,7 @@ gfx_init();
/* Call into mainboard. */ - mainboard_romstage_entry(&rp); + mainboard_romstage_entry_rp(&rp);
if (CONFIG(SMM_TSEG)) smm_list_regions();
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)