Change in coreboot[master]: sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40347 )
Change subject: sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU ......................................................................
sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU
CLKRUN_EN bit available for mobile is reserved on desktop SKUs. PSEUDO_CLKRUN_EN bit available for desktop is reserved for mobile SKUs. Configure these bits accordign to SKU.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I5295eb2bec27c77f800cc2ade9093e97ede47789 --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/40347/1
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 27f45e3..278e90a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -20,6 +20,7 @@ #include "chip.h" #include "pch.h" #include "nvs.h" +#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> @@ -373,7 +374,12 @@ RCBA32_AND_OR(DMIC, ~0UL, 0xf);
reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 2) | (1 << 11); + reg16 &= ~(3 << 2); /* Clear CLKRUN bits for mobile and desktop */ + if (get_platform_type() == PLATFORM_MOBILE) + reg16 |= (1 << 2); /* CLKRUN_EN for mobile */ + else if (get_platform_type() == PLATFORM_DESKTOP_SERVER) + reg16 |= (1 << 3); /* PSEUDO_CLKRUN_EN for desktop */ + reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40347 )
Change subject: sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40347 )
Change subject: sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU ......................................................................
sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU
CLKRUN_EN bit available for mobile is reserved on desktop SKUs. PSEUDO_CLKRUN_EN bit available for desktop is reserved for mobile SKUs. Configure these bits accordign to SKU.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I5295eb2bec27c77f800cc2ade9093e97ede47789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40347 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 7 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 27f45e3..278e90a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -20,6 +20,7 @@ #include "chip.h" #include "pch.h" #include "nvs.h" +#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> @@ -373,7 +374,12 @@ RCBA32_AND_OR(DMIC, ~0UL, 0xf);
reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 |= (1 << 2) | (1 << 11); + reg16 &= ~(3 << 2); /* Clear CLKRUN bits for mobile and desktop */ + if (get_platform_type() == PLATFORM_MOBILE) + reg16 |= (1 << 2); /* CLKRUN_EN for mobile */ + else if (get_platform_type() == PLATFORM_DESKTOP_SERVER) + reg16 |= (1 << 3); /* PSEUDO_CLKRUN_EN for desktop */ + reg16 |= (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40347 )
Change subject: sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2341 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2340 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2339
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Michał Żygowski (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)