Change in coreboot[master]: mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16 - coreboot-gerrit

17 Nov 2019

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36889 )
Change subject: mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16
......................................................................
mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16
This bit is used to indicate xHCI routing across reboots. If anything,
coreboot should act on it, not set it during boot. ASL code would be
supposed to set it.
Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a
Signed-off-by: Nico Huber nico.h@gmx.de
---
M src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
M src/mainboard/lenovo/s230u/early_init.c
M src/mainboard/lenovo/t420/early_init.c
M src/mainboard/lenovo/t420s/early_init.c
M src/mainboard/lenovo/t430s/Makefile.inc
D src/mainboard/lenovo/t430s/early_init.c
M src/mainboard/lenovo/t520/early_init.c
M src/mainboard/lenovo/t530/early_init.c
M src/mainboard/lenovo/x1_carbon_gen1/early_init.c
M src/mainboard/lenovo/x220/early_init.c
M src/mainboard/lenovo/x230/early_init.c
11 files changed, 0 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36889/1

diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
index 0a863ff..65616ff 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
@@ -26,11 +26,6 @@
 #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
 #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 void bootblock_mainboard_early_init(void)
 {
    /* Initialize SuperIO */
diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c
index 6bc92b2..7c302b8 100644
--- a/src/mainboard/lenovo/s230u/early_init.c
+++ b/src/mainboard/lenovo/s230u/early_init.c
@@ -29,8 +29,6 @@
void mainboard_pch_lpc_setup(void)
 {
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-
    /* Memory map KB9012 EC registers */
    pci_write_config32(
    	PCH_LPC_DEV, LGMR,
diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c
index 50e6258..8afd1501 100644
--- a/src/mainboard/lenovo/t420/early_init.c
+++ b/src/mainboard/lenovo/t420/early_init.c
@@ -49,11 +49,6 @@
    pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
 const struct southbridge_usb_port mainboard_usb_ports[] = {
    { 1, 1,  0 }, /* P0: system port 4, OC0 */
diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c
index 1357a0a..e2cdebf 100644
--- a/src/mainboard/lenovo/t420s/early_init.c
+++ b/src/mainboard/lenovo/t420s/early_init.c
@@ -49,11 +49,6 @@
    pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
    { 0, 1, -1 }, /* P0 empty */
    { 1, 1,  1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */
diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc
index d0e69a8..425047f 100644
--- a/src/mainboard/lenovo/t430s/Makefile.inc
+++ b/src/mainboard/lenovo/t430s/Makefile.inc
@@ -20,5 +20,3 @@
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
 subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd
-bootblock-y += early_init.c
-romstage-y += early_init.c
diff --git a/src/mainboard/lenovo/t430s/early_init.c b/src/mainboard/lenovo/t430s/early_init.c
deleted file mode 100644
index 0757c06..0000000
--- a/src/mainboard/lenovo/t430s/early_init.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_ops.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c
index cfa69b7..ad8e152 100644
--- a/src/mainboard/lenovo/t520/early_init.c
+++ b/src/mainboard/lenovo/t520/early_init.c
@@ -51,11 +51,6 @@
    pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
    { 1, 1, 0 }, /* P0 left dual conn, OC 0 */
    { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */
diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c
index 34c61e4..aeb27a6 100644
--- a/src/mainboard/lenovo/t530/early_init.c
+++ b/src/mainboard/lenovo/t530/early_init.c
@@ -51,11 +51,6 @@
    pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 void mainboard_early_init(int s3resume)
 {
    hybrid_graphics_init();
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
index c70b21d..c65b454 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c
@@ -28,11 +28,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <cbfs.h>
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
    /* enabled, current, OC pin */
    { 0, 3, 0 }, /* P00 disconnected */
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index 8ee807c..7a29d18 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -27,11 +27,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/x86/msr.h>
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
    struct pei_data pei_data_template = {
diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c
index b737e7d..a6853a1 100644
--- a/src/mainboard/lenovo/x230/early_init.c
+++ b/src/mainboard/lenovo/x230/early_init.c
@@ -24,11 +24,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
    { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
    { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a
Gerrit-Change-Number: 36889
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber nico.h@gmx.de
Gerrit-Reviewer: Alexander Couzens lynxis@fe80.eu
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Nico Huber nico.h@gmx.de
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    