Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h 2 files changed, 57 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/1
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 73181cf..fd53217 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -33,6 +33,10 @@
#include "spi.h"
+#if (!ICH7_SPI && !ICH9_SPI && !BYT_BSW_SPI) +#error "Unsupported SPI controller! +#endif + #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ @@ -271,6 +275,30 @@ #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) #endif
+static void *get_spi_bar(void) +{ + uint32_t rcba; /* Root Complex Register Block */ + uint32_t sbase; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = PCI_DEV(0, 31, 0); +#else + struct device *dev = pcidev_on_root(31, 0); +#endif + if (ICH7_SPI) { + rcba = pci_read_config32(dev, 0xf0); + return (void *)((rcba & 0xffffc000) + 0x3020); + } + if (BYT_BSW_SPI) { + sbase = pci_read_config32(dev, 0x52); + sbase &= ~0x1ff; + return (void *)sbase; + } + if (ICH9_SPI) { + rcba = pci_read_config32(dev, 0xf0); + return (void *)((rcba & 0xffffc000) + 0x3800); + } +} + void spi_init(void) { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); @@ -281,17 +309,8 @@ struct ich7_spi_regs *ich7_spi; uint16_t hsfs;
-#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 31, 0); -#else - struct device *dev = pcidev_on_root(31, 0); -#endif - - rcba = pci_read_config32(dev, 0xf0); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); - if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + if (ICH7_SPI) { + ich7_spi = get_spi_bar(); cntlr->ich7_spi = ich7_spi; cntlr->opmenu = ich7_spi->opmenu; cntlr->menubytes = sizeof(ich7_spi->opmenu); @@ -306,7 +325,7 @@ cntlr->fpr = &ich7_spi->pbr[0]; cntlr->fpr_max = 3; } else { - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); + ich9_spi = get_spi_bar(); cntlr->ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); cntlr->hsfs = hsfs; @@ -333,11 +352,20 @@
ich_set_bbar(0);
- /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + if (BYT_BSW_SPI) { + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = readl_(ich9_spi + 0xfc); + bios_cntl |= 1; + writel_(bios_cntl, ich9_spi + 0xfc); + } + + if (ICH7_SPI || ICH9_SPI) { + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = pci_read_config8(dev, 0xdc); + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + } }
static int spi_locked(void) diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410c..84e183e 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -32,6 +32,18 @@ struct intel_spi_op ops[8]; };
+#define ICH7_SPI CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#define ICH9_SPI (CONFIG(SOUTHBRIDGE_INTEL_I82801IX) || \ + CONFIG(SOUTHBRIDGE_INTEL_I82801JX) || \ + CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK) || \ + CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \ + CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) || \ + CONFIG(SOC_INTEL_BROADWELL) || \ + CONFIG(SOC_INTEL_BROADWELL_DE)) +#define BYT_BSW_SPI (CONFIG(SOC_INTEL_BAYTRAIL) || \ + CONFIG(SOC_INTEL_FSP_BAYTRAIL) || \ + CONFIG(SOC_INTEL_BRASWELL)) + void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config);
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36342
to look at the new patch set (#2).
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h 2 files changed, 57 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36342
to look at the new patch set (#3).
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h 2 files changed, 58 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/3
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... PS3, Line 292: sbase = pci_read_config32(dev, 0x52); Need to be 0x54 for Braswell.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... PS3, Line 281: uint32_t sbase; Please make use of `uintptr_t`. People want to introduce long-mode support, I've heard oO
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... PS3, Line 292: sbase = pci_read_config32(dev, 0x52);
Need to be 0x54 for Braswell.
Would using defines (like SBASE in SoC) make code mode readable?
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36342
to look at the new patch set (#4).
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h 2 files changed, 54 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/4
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... PS3, Line 281: uint32_t sbase;
Please make use of `uintptr_t`. […]
Done
https://review.coreboot.org/c/coreboot/+/36342/3/src/southbridge/intel/commo... PS3, Line 292: sbase = pci_read_config32(dev, 0x52);
Would using defines (like SBASE in SoC) make code mode readable?
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 5: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.h:
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... PS5, Line 46: CONFIG(SOC_INTEL_BRASWELL)) Alternatively, we could add Kconfig flags and select them from each chipset.
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... PS5, Line 38: #endif Wouldn't be necessary if using Kconfig for the flags.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 5: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... PS5, Line 285: #ifdef __SIMPLE_DEVICE__ : pci_devfn_t dev = PCI_DEV(0, 31, 0); : #else : struct device *dev = pcidev_on_root(31, 0); : #endif Why not pass `dev` in instead?
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36342
to look at the new patch set (#6).
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 9 files changed, 49 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/6
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... PS5, Line 285: #ifdef __SIMPLE_DEVICE__ : pci_devfn_t dev = PCI_DEV(0, 31, 0); : #else : struct device *dev = pcidev_on_root(31, 0); : #endif
Why not pass `dev` in instead?
Done
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.h:
https://review.coreboot.org/c/coreboot/+/36342/5/src/southbridge/intel/commo... PS5, Line 46: CONFIG(SOC_INTEL_BRASWELL))
Alternatively, we could add Kconfig flags and select them from […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... File src/southbridge/intel/common/Kconfig:
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... PS6, Line 32: Idea (for follow-up?): Add `config ..._SPI_ICH7` and `select ..._COMMON_SPI` from each? Then we'd need one `select` less per platform.
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... PS6, Line 281: #endif Does this file use `struct device` for anything but pci_*_config*()? Can't we just `#define __SIMPLE_DEVICE__`?
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36342
to look at the new patch set (#7).
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/broadwell/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 9 files changed, 55 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/36342/7
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... File src/southbridge/intel/common/Kconfig:
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... PS6, Line 32:
Idea (for follow-up?): Add `config ..._SPI_ICH7` and `select ..._COMMON_SPI` […]
Done
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... File src/southbridge/intel/common/spi.c:
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... PS6, Line 281: #endif
Does this file use `struct device` for anything but pci_*_config*()? […]
Done in CB:37079
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... File src/southbridge/intel/common/Kconfig:
https://review.coreboot.org/c/coreboot/+/36342/6/src/southbridge/intel/commo... PS6, Line 32:
Done
Thanks :)
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36342 )
Change subject: sb/intel/common/spi: Add Baytrail/Braswell support ......................................................................
sb/intel/common/spi: Add Baytrail/Braswell support
The mechanism for getting the SPIBAR is little different.
Tested on Intel Minnowboard Turbot.
Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/broadwell/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 9 files changed, 55 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 07bcf22..21c9b6f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,7 @@ select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1c7e9b7..8b8f6b3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -27,7 +27,7 @@ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 18bcd2e..d1b6bf6 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -24,6 +24,18 @@ select SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES
+config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + +config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + +config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a84a0df..4926df9 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -271,11 +271,36 @@ #define MENU_BYTES member_size(struct ich9_spi_regs, opmenu) #endif
+#define RCBA 0xf0 +#define SBASE 0x54 + +#ifdef __SIMPLE_DEVICE__ +static void *get_spi_bar(pci_devfn_t dev) +#else +static void *get_spi_bar(struct device *dev) +#endif +{ + uintptr_t rcba; /* Root Complex Register Block */ + uintptr_t sbase; + + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { + rcba = pci_read_config32(dev, RCBA); + return (void *)((rcba & 0xffffc000) + 0x3020); + } + if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT)) { + sbase = pci_read_config32(dev, SBASE); + sbase &= ~0x1ff; + return (void *)sbase; + } + if (CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { + rcba = pci_read_config32(dev, RCBA); + return (void *)((rcba & 0xffffc000) + 0x3800); + } +} + void spi_init(void) { struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; @@ -287,11 +312,8 @@ struct device *dev = pcidev_on_root(31, 0); #endif
- rcba = pci_read_config32(dev, 0xf0); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) { - ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + ich7_spi = get_spi_bar(dev); cntlr->ich7_spi = ich7_spi; cntlr->opmenu = ich7_spi->opmenu; cntlr->menubytes = sizeof(ich7_spi->opmenu); @@ -306,7 +328,7 @@ cntlr->fpr = &ich7_spi->pbr[0]; cntlr->fpr_max = 3; } else { - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); + ich9_spi = get_spi_bar(dev); cntlr->ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); cntlr->hsfs = hsfs; @@ -333,11 +355,13 @@
ich_set_bbar(0);
- /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { + /* Disable the BIOS write protect so write commands are allowed. */ + bios_cntl = pci_read_config8(dev, 0xdc); + /* Deassert SMM BIOS Write Protect Disable. */ + bios_cntl &= ~(1 << 5); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + } }
static int spi_locked(void) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d95fc2..deb1129 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -22,7 +22,7 @@ select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select HAVE_INTEL_CHIPSET_LOCKDOWN diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8363978..1e2ee47 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -17,7 +17,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 161290f..0e756a8 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -17,7 +17,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index f9723fb..f94e7a8 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -29,7 +29,7 @@ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index ef071f2..87f7298 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -22,7 +22,7 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
-
Arthur Heymans (Code Review) -
Frans Hendriks (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)