Attention is currently required from: Reka Norman, Jon Murphy, Tim Wawrzynczak, Amanda Hwang, Ivy Jian.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 )
Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
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Patch Set 1:
(2 comments)
Patchset:
PS1:
Can you please rebase on top of CB:62387
File spd/lp5/memory_parts.json:
https://review.coreboot.org/c/coreboot/+/62542/comment/4bc0a975_08778cb7
PS1, Line 54: "name": "MT62F2G32D8DR-031 WT:B",
I think this is correct for ADL at least. […]
Ack. IIUC, there are 2 ways to handle this memory part
1) 4 channels of x8bits(Byte 6 - 0xF9, Byte 12 - 0x9)
2) Through byte mode, combine x8 bits from 2 dies into x16 bits. Then there will be 2 channels(Byte 6 - 0xF5, Byte 12 - 0x49)
Let us go with option 1 for now. As per the reference SPDs shared by AMD, they advice option 2. I will double check with AMD and update if needed.
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